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VM: support cpu registers
This commit is contained in:
Irmen de Jong
parent
627ed51a1b
commit
11d87e4725
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@ -3,7 +3,7 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- IR/VM: actually support the physical cpu registers and status flags in the STORECPU and LOADCPU opcodes.
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- Join codeAst and codeCore modules?
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- IR: option to save IR in file
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- Replace existing vm codegen by expericodegen, expericodegen just stops at saving IR in file.
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- vm: implement remaining sin/cos functions in virtual/math.p8 and merge tables
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@ -3,19 +3,31 @@ main {
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sub start() {
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uword @shared slab1 = memory("slab 1", 2000, 0)
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uword @shared slab2 = memory("slab 1", 2000, 0)
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uword @shared slab3 = memory("other # slab", 2000, 64)
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%asm {{
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loadcpu.b r1,_a
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loadcpu.b r1,_x
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loadcpu.b r1,_y
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loadcpu.w r1,_ax
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loadcpu.w r1,_ay
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loadcpu.w r1,_xy
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loadcpu.b r1,_pc
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loadcpu.b r1,_pn
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loadcpu.b r1,_pz
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loadcpu.w r1,_r0
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loadcpu.w r1,_r15
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uword total = slab1+slab2+slab3
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txt.print_uw(slab1)
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txt.nl()
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txt.print_uw(slab2)
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txt.nl()
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txt.print_uw(slab3)
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txt.nl()
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txt.print_uw(total)
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txt.nl()
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storezcpu.b _a
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storezcpu.b _x
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storezcpu.b _y
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storezcpu.w _ax
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storezcpu.w _ay
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storezcpu.w _xy
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storezcpu.b _pc
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storezcpu.b _pn
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storezcpu.b _pz
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storezcpu.b _r0
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storezcpu.w _r15
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}}
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}
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}
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@ -7,6 +7,7 @@ import prog8.intermediate.*
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class Assembler {
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private val symbolAddresses = mutableMapOf<String, Int>()
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private val placeholders = mutableMapOf<Int, String>()
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var cx16virtualregBaseAdress = 0xff02
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init {
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require(instructionFormats.size== Opcode.values().size) {
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@ -25,6 +26,9 @@ class Assembler {
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throw IllegalArgumentException("invalid line $line")
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else {
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val (name, addrStr, datatype, arrayspec, values) = match.destructured
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if(name=="cx16.r0") {
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cx16virtualregBaseAdress = addrStr.toInt()
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}
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val numArrayElts = if(arrayspec.isBlank()) 1 else arrayspec.substring(1, arrayspec.length-1).toInt()
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var address = parseValue(Opcode.LOADCPU, addrStr, 0).toInt()
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symbolAddresses[name] = address
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@ -250,17 +254,18 @@ class Assembler {
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floatValue = value!!
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if(opcode in OpcodesForCpuRegisters) {
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val reg=rest.split(',').last().lowercase()
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val regStr = rest.split(',').last().lowercase().trim()
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val reg = if(regStr.startsWith('_')) regStr.substring(1) else regStr
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if(reg !in setOf(
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"_a", "_x", "_y",
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"_ax", "_ay", "_xy",
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"_r0", "_r1", "_r2", "_r3",
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"_r4", "_r5", "_r6", "_r7",
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"_r8", "_r9", "_r10","_r11",
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"_r12", "_r13", "_r14", "_r15",
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"_pc", "_pz", "_pv","_pn"))
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"a", "x", "y",
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"ax", "ay", "xy",
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"r0", "r1", "r2", "r3",
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"r4", "r5", "r6", "r7",
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"r8", "r9", "r10","r11",
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"r12", "r13", "r14", "r15",
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"pc", "pz", "pv","pn"))
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throw IllegalArgumentException("invalid cpu reg: $reg")
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program.add(Instruction(opcode, type, reg1, labelSymbol = listOf(reg.substring(1))))
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program.add(Instruction(opcode, type, reg1, labelSymbol = listOf(reg)))
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} else {
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program.add(Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, intValue, floatValue))
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}
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@ -38,6 +38,6 @@ return"""
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assembler.initializeMemory(memsrc, memory)
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val program = assembler.assembleProgram(src)
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val vm = VirtualMachine(memory, program)
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val vm = VirtualMachine(memory, program, assembler.cx16virtualregBaseAdress)
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vm.run()
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}
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@ -3,14 +3,21 @@ package prog8.vm
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/**
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* 65536 virtual integer registers of 16 bits wide.
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* 65536 virtual float registers of 32 bits wide.
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* A,X and Y "physical" 6502 registers.
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*/
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class Registers {
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private val registers = Array<UShort>(65536) { 0u }
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private val floatRegisters = Array(65535) { 0f }
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var cpuA: UByte = 0u
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var cpuX: UByte = 0u
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var cpuY: UByte = 0u
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fun reset() {
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registers.fill(0u)
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floatRegisters.fill(0f)
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cpuA = 0u
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cpuX = 0u
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cpuY = 0u
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}
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fun setUB(reg: Int, value: UByte) {
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@ -31,7 +31,7 @@ class BreakpointException(val pc: Int): Exception()
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@Suppress("FunctionName")
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class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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class VirtualMachine(val memory: Memory, program: List<Instruction>, val cx16virtualregsBaseAddress: Int) {
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val registers = Registers()
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val program: Array<Instruction> = program.toTypedArray()
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val callStack = Stack<Int>()
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@ -305,14 +305,39 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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}
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private fun InsLOADCPU(i: Instruction) {
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println("VM:TODO: load reg ${i.reg1} from cpu register ${i.labelSymbol}") // TODO
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val reg = i.labelSymbol!!.single()
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val value: UInt
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if(reg.startsWith('r')) {
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val regnum = reg.substring(1).toInt()
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val regAddr = cx16virtualregsBaseAddress + regnum*2
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value = memory.getUW(regAddr).toUInt()
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} else {
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value = when(reg) {
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"a" -> registers.cpuA.toUInt()
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"x" -> registers.cpuX.toUInt()
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"y" -> registers.cpuY.toUInt()
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"ax" -> (registers.cpuA.toUInt() shl 8) or registers.cpuX.toUInt()
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"ay" -> (registers.cpuA.toUInt() shl 8) or registers.cpuY.toUInt()
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"xy" -> (registers.cpuX.toUInt() shl 8) or registers.cpuY.toUInt()
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"pc" -> if(statusCarry) 1u else 0u
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"pz" -> if(statusZero) 1u else 0u
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"pn" -> if(statusNegative) 1u else 0u
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"pv" -> throw IllegalArgumentException("overflow status register not supported in VM")
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else -> throw IllegalArgumentException("invalid cpu reg")
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}
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}
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, value.toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, value.toUShort())
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else -> throw java.lang.IllegalArgumentException("invalid cpu reg type")
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}
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pc++
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}
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private fun InsSTORECPU(i: Instruction) {
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val value: UShort = when(i.type!!) {
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VmDataType.BYTE -> registers.getUB(i.reg1!!).toUShort()
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VmDataType.WORD -> registers.getUW(i.reg1!!)
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val value: UInt = when(i.type!!) {
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VmDataType.BYTE -> registers.getUB(i.reg1!!).toUInt()
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VmDataType.WORD -> registers.getUW(i.reg1!!).toUInt()
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VmDataType.FLOAT -> throw IllegalArgumentException("there are no float cpu registers")
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}
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StoreCPU(value, i.type!!, i.labelSymbol!!.single())
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@ -324,8 +349,39 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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}
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private fun StoreCPU(value: UShort, dt: VmDataType, regStr: String) {
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println("VM:TODO: store a value into cpu register $regStr") // TODO
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private fun StoreCPU(value: UInt, dt: VmDataType, regStr: String) {
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if(regStr.startsWith('r')) {
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val regnum = regStr.substring(1).toInt()
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val regAddr = cx16virtualregsBaseAddress + regnum*2
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when(dt) {
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VmDataType.BYTE -> memory.setUB(regAddr, value.toUByte())
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VmDataType.WORD -> memory.setUW(regAddr, value.toUShort())
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else -> throw IllegalArgumentException("invalid reg dt")
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}
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} else {
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when (regStr) {
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"a" -> registers.cpuA = value.toUByte()
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"x" -> registers.cpuX = value.toUByte()
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"y" -> registers.cpuY = value.toUByte()
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"ax" -> {
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registers.cpuA = (value and 255u).toUByte()
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registers.cpuX = (value shr 8).toUByte()
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}
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"ay" -> {
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registers.cpuA = (value and 255u).toUByte()
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registers.cpuY = (value shr 8).toUByte()
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}
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"xy" -> {
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registers.cpuX = (value and 255u).toUByte()
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registers.cpuY = (value shr 8).toUByte()
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}
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"pc" -> statusCarry = value == 1u
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"pz" -> statusZero = value == 1u
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"pn" -> statusNegative = value == 1u
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"pv" -> throw IllegalArgumentException("overflow status register not supported in VM")
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else -> throw IllegalArgumentException("invalid cpu reg")
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}
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}
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}
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private fun InsLOAD(i: Instruction) {
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@ -2055,7 +2111,7 @@ class VmRunner: IVirtualMachineRunner {
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val assembler = Assembler()
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assembler.initializeMemory(memsrc, memory)
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val program = assembler.assembleProgram(programsrc)
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val vm = VirtualMachine(memory, program)
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val vm = VirtualMachine(memory, program, assembler.cx16virtualregBaseAdress)
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vm.run(throttle = true)
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}
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}
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