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vm: fix assignment to array

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This commit is contained in:
Irmen de Jong 2022-05-11 15:26:54 +02:00
parent d43ad849d1
commit 14e36f1362
3 changed files with 37 additions and 18 deletions
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29
codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt
View File

@ -646,25 +646,34 @@ class CodeGen(internal val program: PtProgram,
var variableAddr = allocations.get(variable)
val itemsize = program.memsizer.memorySize(array.type)
val fixedIndex = constIntValue(array.index)
val vmDtArrayIdx = vmType(array.type)
// TODO floating point array incorrect?
if(zero) {
if(fixedIndex!=null) {
variableAddr += fixedIndex*itemsize
code += VmCodeInstruction(Opcode.STOREZM, vmDtArrayIdx, value=variableAddr)
code += VmCodeInstruction(Opcode.STOREZM, VmDataType.FLOAT, value=variableAddr)
} else {
val indexReg = vmRegisters.nextFree()
code += expressionEval.translateExpression(array.index, indexReg, -1)
code += VmCodeInstruction(Opcode.STOREZX, vmDtArrayIdx, reg1=indexReg, value=variableAddr)
code += VmCodeInstruction(Opcode.STOREZX, VmDataType.FLOAT, reg1=indexReg, value=variableAddr)
}
} else {
if(fixedIndex!=null) {
variableAddr += fixedIndex*itemsize
code += VmCodeInstruction(Opcode.STOREM, vmDtArrayIdx, reg1 = resultRegister, value=variableAddr)
if(vmDt==VmDataType.FLOAT) {
if(fixedIndex!=null) {
variableAddr += fixedIndex*itemsize
code += VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value=variableAddr)
} else {
val indexReg = vmRegisters.nextFree()
code += expressionEval.translateExpression(array.index, indexReg, -1)
code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
}
} else {
val indexReg = vmRegisters.nextFree()
code += expressionEval.translateExpression(array.index, indexReg, -1)
code += VmCodeInstruction(Opcode.STOREX, vmDtArrayIdx, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
if(fixedIndex!=null) {
variableAddr += fixedIndex*itemsize
code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value=variableAddr)
} else {
val indexReg = vmRegisters.nextFree()
code += expressionEval.translateExpression(array.index, indexReg, -1)
code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
}
}
}
}

1
docs/source/todo.rst
View File

@ -3,7 +3,6 @@ TODO
For next release
^^^^^^^^^^^^^^^^
- vm: assignment to float array is not correct? also zero?
- vm: use more instructions in codegen: shift one
- vm: use more instructions in codegen: branching
- vm: add more instructions operating directly on memory instead of only registers?

25
examples/test.p8
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@ -1,5 +1,6 @@
%import textio
%import math
%import floats
%zeropage dontuse
@ -20,15 +21,25 @@ main {
; return first * second
; }
sub ding(uword arg) {
arg++
txt.print_uw(arg)
}
sub start() {
ding(0)
uword[] arrayuw = [1111,2222,3333,4444]
txt.print_uw(arrayuw[1])
txt.nl()
ding(2)
arrayuw[1] = 9999
txt.print_uw(arrayuw[1])
txt.nl()
arrayuw[1] = 0
txt.print_uw(arrayuw[1])
txt.nl()
float[] array = [1.1, 2.2, 3.3, 4.4]
floats.print_f(array[1])
txt.nl()
array[1] = 99.99
floats.print_f(array[1])
txt.nl()
array[1] = 0
floats.print_f(array[1])
txt.nl()
; ubyte value = inline_candidate()