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vm: fix assignment to array
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d43ad849d1
commit
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@ -646,25 +646,34 @@ class CodeGen(internal val program: PtProgram,
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var variableAddr = allocations.get(variable)
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var variableAddr = allocations.get(variable)
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val itemsize = program.memsizer.memorySize(array.type)
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val itemsize = program.memsizer.memorySize(array.type)
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val fixedIndex = constIntValue(array.index)
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val fixedIndex = constIntValue(array.index)
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val vmDtArrayIdx = vmType(array.type)
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// TODO floating point array incorrect?
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if(zero) {
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if(zero) {
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if(fixedIndex!=null) {
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if(fixedIndex!=null) {
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variableAddr += fixedIndex*itemsize
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variableAddr += fixedIndex*itemsize
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code += VmCodeInstruction(Opcode.STOREZM, vmDtArrayIdx, value=variableAddr)
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code += VmCodeInstruction(Opcode.STOREZM, VmDataType.FLOAT, value=variableAddr)
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} else {
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} else {
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val indexReg = vmRegisters.nextFree()
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val indexReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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code += VmCodeInstruction(Opcode.STOREZX, vmDtArrayIdx, reg1=indexReg, value=variableAddr)
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code += VmCodeInstruction(Opcode.STOREZX, VmDataType.FLOAT, reg1=indexReg, value=variableAddr)
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}
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}
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} else {
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} else {
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if(fixedIndex!=null) {
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if(vmDt==VmDataType.FLOAT) {
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variableAddr += fixedIndex*itemsize
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if(fixedIndex!=null) {
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code += VmCodeInstruction(Opcode.STOREM, vmDtArrayIdx, reg1 = resultRegister, value=variableAddr)
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variableAddr += fixedIndex*itemsize
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code += VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value=variableAddr)
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} else {
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val indexReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
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}
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} else {
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} else {
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val indexReg = vmRegisters.nextFree()
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if(fixedIndex!=null) {
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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variableAddr += fixedIndex*itemsize
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code += VmCodeInstruction(Opcode.STOREX, vmDtArrayIdx, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value=variableAddr)
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} else {
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val indexReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
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}
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}
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}
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}
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}
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}
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}
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@ -3,7 +3,6 @@ TODO
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For next release
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For next release
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^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^
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- vm: assignment to float array is not correct? also zero?
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- vm: use more instructions in codegen: shift one
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- vm: use more instructions in codegen: shift one
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- vm: use more instructions in codegen: branching
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- vm: use more instructions in codegen: branching
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- vm: add more instructions operating directly on memory instead of only registers?
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- vm: add more instructions operating directly on memory instead of only registers?
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@ -1,5 +1,6 @@
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%import textio
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%import textio
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%import math
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%import math
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%import floats
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%zeropage dontuse
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%zeropage dontuse
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@ -20,15 +21,25 @@ main {
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; return first * second
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; return first * second
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; }
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; }
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sub ding(uword arg) {
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arg++
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txt.print_uw(arg)
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}
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sub start() {
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sub start() {
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ding(0)
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uword[] arrayuw = [1111,2222,3333,4444]
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txt.print_uw(arrayuw[1])
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txt.nl()
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txt.nl()
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ding(2)
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arrayuw[1] = 9999
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txt.print_uw(arrayuw[1])
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txt.nl()
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arrayuw[1] = 0
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txt.print_uw(arrayuw[1])
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txt.nl()
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float[] array = [1.1, 2.2, 3.3, 4.4]
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floats.print_f(array[1])
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txt.nl()
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array[1] = 99.99
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floats.print_f(array[1])
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txt.nl()
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array[1] = 0
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floats.print_f(array[1])
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txt.nl()
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txt.nl()
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; ubyte value = inline_candidate()
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; ubyte value = inline_candidate()
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