fix ast source gen for romsub

This commit is contained in:
Irmen de Jong 2024-11-03 15:04:53 +01:00
parent 9f84aa5fb2
commit 178e60bba0
2 changed files with 7 additions and 5 deletions

View File

@ -1716,7 +1716,7 @@ class IRCodeGen(
) )
irBlock += IRAsmSubroutine( irBlock += IRAsmSubroutine(
child.name, child.name,
child.address, null,
child.clobbers, child.clobbers,
child.parameters.map { IRAsmSubroutine.IRAsmParam(it.first, it.second.type) }, // note: the name of the asmsub param is not used here anymore child.parameters.map { IRAsmSubroutine.IRAsmParam(it.first, it.second.type) }, // note: the name of the asmsub param is not used here anymore
child.returns.map { IRAsmSubroutine.IRAsmParam(it.first, it.second)}, child.returns.map { IRAsmSubroutine.IRAsmParam(it.first, it.second)},

View File

@ -180,6 +180,10 @@ class AstToSourceTextConverter(val output: (text: String) -> Unit, val program:
if(subroutine.inline) if(subroutine.inline)
output("inline ") output("inline ")
if(subroutine.isAsmSubroutine) { if(subroutine.isAsmSubroutine) {
if(subroutine.asmAddress!=null) {
output("romsub ${subroutine.asmAddress.toHex()} = ${subroutine.name} (")
}
else
output("asmsub ${subroutine.name} (") output("asmsub ${subroutine.name} (")
for(param in subroutine.parameters.zip(subroutine.asmParameterRegisters)) { for(param in subroutine.parameters.zip(subroutine.asmParameterRegisters)) {
val reg = val reg =
@ -227,9 +231,7 @@ class AstToSourceTextConverter(val output: (text: String) -> Unit, val program:
output("-> $rts ") output("-> $rts ")
} }
} }
if(subroutine.asmAddress!=null) if (subroutine.asmAddress == null) {
outputln("= ${subroutine.asmAddress.toHex()}")
else {
outputln("{ ") outputln("{ ")
scopelevel++ scopelevel++
outputStatements(subroutine.statements.filter { it !is VarDecl || it.origin!=VarDeclOrigin.SUBROUTINEPARAM}) outputStatements(subroutine.statements.filter { it !is VarDecl || it.origin!=VarDeclOrigin.SUBROUTINEPARAM})