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fix ast source gen for romsub
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commit
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@ -1716,7 +1716,7 @@ class IRCodeGen(
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)
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)
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irBlock += IRAsmSubroutine(
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irBlock += IRAsmSubroutine(
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child.name,
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child.name,
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child.address,
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null,
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child.clobbers,
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child.clobbers,
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child.parameters.map { IRAsmSubroutine.IRAsmParam(it.first, it.second.type) }, // note: the name of the asmsub param is not used here anymore
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child.parameters.map { IRAsmSubroutine.IRAsmParam(it.first, it.second.type) }, // note: the name of the asmsub param is not used here anymore
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child.returns.map { IRAsmSubroutine.IRAsmParam(it.first, it.second)},
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child.returns.map { IRAsmSubroutine.IRAsmParam(it.first, it.second)},
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@ -180,6 +180,10 @@ class AstToSourceTextConverter(val output: (text: String) -> Unit, val program:
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if(subroutine.inline)
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if(subroutine.inline)
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output("inline ")
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output("inline ")
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if(subroutine.isAsmSubroutine) {
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if(subroutine.isAsmSubroutine) {
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if(subroutine.asmAddress!=null) {
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output("romsub ${subroutine.asmAddress.toHex()} = ${subroutine.name} (")
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}
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else
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output("asmsub ${subroutine.name} (")
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output("asmsub ${subroutine.name} (")
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for(param in subroutine.parameters.zip(subroutine.asmParameterRegisters)) {
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for(param in subroutine.parameters.zip(subroutine.asmParameterRegisters)) {
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val reg =
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val reg =
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@ -227,9 +231,7 @@ class AstToSourceTextConverter(val output: (text: String) -> Unit, val program:
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output("-> $rts ")
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output("-> $rts ")
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}
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}
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}
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}
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if(subroutine.asmAddress!=null)
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if (subroutine.asmAddress == null) {
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outputln("= ${subroutine.asmAddress.toHex()}")
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else {
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outputln("{ ")
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outputln("{ ")
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scopelevel++
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scopelevel++
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outputStatements(subroutine.statements.filter { it !is VarDecl || it.origin!=VarDeclOrigin.SUBROUTINEPARAM})
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outputStatements(subroutine.statements.filter { it !is VarDecl || it.origin!=VarDeclOrigin.SUBROUTINEPARAM})
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