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tweak vm codegen
This commit is contained in:
Irmen de Jong
parent
93ce74eeb1
commit
1e441c2ddf
@ -1,9 +1,7 @@
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package prog8.codegen.virtual
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.SignedDatatypes
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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@ -33,7 +31,9 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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else
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fallbackAssign(assignment)
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} else if(array!=null) {
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// TODO in-place array element assignment?
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// NOTE: naive fallback assignment here will sometimes generate code that loads the index value multiple times
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// in a register. It's way too much work to optimize that here - instead, we trust that the generated IL assembly
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// will be optimized later and have the double assignments removed.
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fallbackAssign(assignment)
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} else {
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fallbackAssign(assignment)
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@ -275,15 +275,8 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1=indexReg, value=loopvarAddress)
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code += VmCodeLabel(loopLabel)
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code += translateNode(forLoop.statements)
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if(step<3) {
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code += addConstMem(loopvarDt, loopvarAddress.toUInt(), step)
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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} else {
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// TODO WHY THIS DISTINCTION?
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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code += addConstReg(loopvarDt, indexReg, step)
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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}
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code += addConstMem(loopvarDt, loopvarAddress.toUInt(), step)
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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val branchOpcode = if(loopvar.dt in SignedDatatypes) Opcode.BLES else Opcode.BLE
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code += VmCodeInstruction(branchOpcode, loopvarDt, reg1=indexReg, reg2=endvalueReg, labelSymbol=loopLabel)
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return code
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@ -315,15 +308,8 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1=indexReg, value=loopvarAddress)
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code += VmCodeLabel(loopLabel)
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code += translateNode(forLoop.statements)
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if(step<3) {
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code += addConstMem(loopvarDt, loopvarAddress.toUInt(), step)
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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} else {
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// TODO WHY THIS DISTICTION ?
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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code += addConstReg(loopvarDt, indexReg, step)
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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}
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code += addConstMem(loopvarDt, loopvarAddress.toUInt(), step)
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code += VmCodeInstruction(Opcode.LOADM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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code += if(rangeEndWrapped==0) {
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VmCodeInstruction(Opcode.BNZ, loopvarDt, reg1 = indexReg, labelSymbol = loopLabel)
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} else {
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@ -381,18 +367,13 @@ class CodeGen(internal val program: PtProgram,
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}
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else -> {
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val valueReg = vmRegisters.nextFree()
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val operandReg = vmRegisters.nextFree()
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if(value>0) {
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=operandReg, value=value)
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code += VmCodeInstruction(Opcode.ADDR, dt, reg1 = valueReg, reg2 = operandReg) // TODO USE ADDM?
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=valueReg, value=value)
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code += VmCodeInstruction(Opcode.ADDM, dt, reg1=valueReg, value=address.toInt())
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}
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else {
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=operandReg, value=-value)
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code += VmCodeInstruction(Opcode.SUBR, dt, reg1 = valueReg, reg2 = operandReg) // TODO USE ADDM?
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=valueReg, value=-value)
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code += VmCodeInstruction(Opcode.SUBM, dt, reg1=valueReg, value=address.toInt())
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}
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}
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}
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@ -172,6 +172,7 @@ class VmPeepholeOptimizer(private val vmprog: AssemblyProgram, private val alloc
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// TODO: detect multiple sequential rnd with same reg1, only keep one
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// TODO: detect subsequent same xors/nots/negs, remove the pairs completely as they cancel out
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// TODO: detect multiple same ands, ors; only keep first
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// TODO: (hard) detect multiple registers being assigned the same value (and not changed) - use only 1 of them
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// ...
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}
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return changed
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@ -3,9 +3,6 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- fix the obvious TODOs in CodeGen (vm)
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- vm: AssignmentGen - fix in-place array assign TODO
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...
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@ -2,27 +2,16 @@
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%zeropage basicsafe
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main {
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romsub $ea31 = foobar(uword derp @AY) -> ubyte @A
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romsub $ea33 = foobar2() -> ubyte @A
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romsub $ea33 = foobar3()
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sub subroutine(ubyte subroutineArg) -> ubyte {
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return subroutineArg+22
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}
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asmsub asmsubje(uword arg @AY) -> ubyte @A {
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%asm {{
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rts
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return
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}}
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}
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sub start() {
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ubyte @shared qq0 = subroutine(11)
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ubyte @shared qq1 = foobar(12345)
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ubyte @shared qq2 = foobar2()
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foobar3()
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ubyte[] arr = [1,2,3,4]
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uword pointer
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ubyte ix
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txt.print_ub(qq0)
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arr[ix] = arr[ix]+1
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; arr[3] = arr[3]+1
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; pointer[3] = pointer[3]+1
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txt.print_ub(arr[3])
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}
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}
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@ -102,7 +102,7 @@ add reg1, value - reg1 += value (unsigned + signed)
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addm reg1, address - memory at address += reg1 (unsigned + signed)
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subr reg1, reg2 - reg1 -= reg2 (unsigned + signed)
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sub reg1, value - reg1 -= value (unsigned + signed)
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subm reg1, address - memory at address -= reg2 (unsigned + signed)
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subm reg1, address - memory at address -= reg1 (unsigned + signed)
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mulr reg1, reg2 - unsigned multiply reg1 *= reg2 note: byte*byte->byte, no type extension to word!
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mul reg1, value - unsigned multiply reg1 *= value note: byte*byte->byte, no type extension to word!
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mulm reg1, address - memory at address *= reg2 note: byte*byte->byte, no type extension to word!
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