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rename
This commit is contained in:
Irmen de Jong
parent
39d6d2857e
commit
2340760f53
@ -63,9 +63,9 @@ class IRCodeGen(
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// for instance when a piece of inlined assembly references them.
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val replacements = mutableListOf<Triple<IRCodeChunkBase, Int, UInt>>()
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irProg.blocks.asSequence().flatMap { it.subroutines }.flatMap { it.chunks }.forEach { chunk ->
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chunk.lines.withIndex().forEach {
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(lineIndex, line) -> if(line is IRInstruction) {
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val symbolExpr = line.labelSymbol
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chunk.instructions.withIndex().forEach {
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(idx, instr) -> if(instr is IRInstruction) {
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val symbolExpr = instr.labelSymbol
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if(symbolExpr!=null) {
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val symbol: String
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val index: UInt
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@ -79,7 +79,7 @@ class IRCodeGen(
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}
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val target = symbolTable.flat[symbol.split('.')]
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if (target is StMemVar) {
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replacements.add(Triple(chunk, lineIndex, target.address+index))
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replacements.add(Triple(chunk, idx, target.address+index))
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}
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}
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}
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@ -87,8 +87,8 @@ class IRCodeGen(
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}
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replacements.forEach {
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val old = it.first.lines[it.second] as IRInstruction
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it.first.lines[it.second] = IRInstruction(
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val old = it.first.instructions[it.second] as IRInstruction
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it.first.instructions[it.second] = IRInstruction(
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old.opcode,
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old.type,
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old.reg1,
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@ -10,7 +10,7 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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// we don't optimize Inline Asm chunks here.
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if(chunk is IRCodeChunk) {
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do {
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val indexedInstructions = chunk.lines.withIndex()
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val indexedInstructions = chunk.instructions.withIndex()
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.filter { it.value is IRInstruction }
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.map { IndexedValue(it.index, it.value as IRInstruction) }
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val changed = removeNops(chunk, indexedInstructions)
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@ -51,7 +51,7 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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chunks += sub.chunks[0]
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for(ix in 1 until sub.chunks.size) {
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if(mayJoin(chunks.last(), sub.chunks[ix]))
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chunks.last().lines += sub.chunks[ix].lines
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chunks.last().instructions += sub.chunks[ix].instructions
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else
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chunks += sub.chunks[ix]
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}
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@ -64,15 +64,15 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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var changed = false
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indexedInstructions.reversed().forEach { (idx, ins) ->
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if(ins.opcode== Opcode.PUSH) {
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if(idx < chunk.lines.size-1) {
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val insAfter = chunk.lines[idx+1] as? IRInstruction
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if(idx < chunk.instructions.size-1) {
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val insAfter = chunk.instructions[idx+1] as? IRInstruction
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if(insAfter!=null && insAfter.opcode == Opcode.POP) {
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if(ins.reg1==insAfter.reg1) {
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chunk.lines.removeAt(idx)
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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chunk.instructions.removeAt(idx)
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} else {
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chunk.lines[idx] = IRInstruction(Opcode.LOADR, ins.type, reg1=insAfter.reg1, reg2=ins.reg1)
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chunk.lines.removeAt(idx+1)
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chunk.instructions[idx] = IRInstruction(Opcode.LOADR, ins.type, reg1=insAfter.reg1, reg2=ins.reg1)
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chunk.instructions.removeAt(idx+1)
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}
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changed = true
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}
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@ -88,18 +88,18 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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var changed = false
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indexedInstructions.reversed().forEach { (idx, ins) ->
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if(ins.opcode== Opcode.SEC || ins.opcode== Opcode.CLC) {
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if(idx < chunk.lines.size-1) {
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val insAfter = chunk.lines[idx+1] as? IRInstruction
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if(idx < chunk.instructions.size-1) {
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val insAfter = chunk.instructions[idx+1] as? IRInstruction
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if(insAfter?.opcode == ins.opcode) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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else if(ins.opcode== Opcode.SEC && insAfter?.opcode== Opcode.CLC) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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else if(ins.opcode== Opcode.CLC && insAfter?.opcode== Opcode.SEC) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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@ -114,19 +114,19 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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val labelSymbol = ins.labelSymbol
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if(ins.opcode== Opcode.JUMP && labelSymbol!=null) {
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// remove jump/branch to label immediately below
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if(idx < chunk.lines.size-1) {
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val label = chunk.lines[idx+1] as? IRCodeLabel
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if(idx < chunk.instructions.size-1) {
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val label = chunk.instructions[idx+1] as? IRCodeLabel
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if(label?.name == labelSymbol) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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}
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// remove useless RETURN
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if(ins.opcode == Opcode.RETURN && idx>0) {
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val previous = chunk.lines[idx-1] as? IRInstruction
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val previous = chunk.instructions[idx-1] as? IRInstruction
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if(previous?.opcode in setOf(Opcode.JUMP, Opcode.JUMPA, Opcode.RETURN)) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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@ -141,47 +141,47 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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when (ins.opcode) {
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Opcode.DIV, Opcode.DIVS, Opcode.MUL, Opcode.MOD -> {
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if (ins.value == 1) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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Opcode.ADD, Opcode.SUB -> {
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if (ins.value == 1) {
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chunk.lines[idx] = IRInstruction(
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chunk.instructions[idx] = IRInstruction(
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if (ins.opcode == Opcode.ADD) Opcode.INC else Opcode.DEC,
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ins.type,
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ins.reg1
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)
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changed = true
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} else if (ins.value == 0) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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Opcode.AND -> {
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if (ins.value == 0) {
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chunk.lines[idx] = IRInstruction(Opcode.LOAD, ins.type, reg1 = ins.reg1, value = 0)
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chunk.instructions[idx] = IRInstruction(Opcode.LOAD, ins.type, reg1 = ins.reg1, value = 0)
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changed = true
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} else if (ins.value == 255 && ins.type == IRDataType.BYTE) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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} else if (ins.value == 65535 && ins.type == IRDataType.WORD) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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Opcode.OR -> {
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if (ins.value == 0) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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} else if ((ins.value == 255 && ins.type == IRDataType.BYTE) || (ins.value == 65535 && ins.type == IRDataType.WORD)) {
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chunk.lines[idx] = IRInstruction(Opcode.LOAD, ins.type, reg1 = ins.reg1, value = ins.value)
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chunk.instructions[idx] = IRInstruction(Opcode.LOAD, ins.type, reg1 = ins.reg1, value = ins.value)
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changed = true
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}
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}
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Opcode.XOR -> {
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if (ins.value == 0) {
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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changed = true
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}
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}
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@ -196,7 +196,7 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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indexedInstructions.reversed().forEach { (idx, ins) ->
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if (ins.opcode == Opcode.NOP) {
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changed = true
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chunk.lines.removeAt(idx)
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chunk.instructions.removeAt(idx)
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}
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}
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return changed
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@ -6,12 +6,12 @@ import prog8.codegen.intermediate.IRPeepholeOptimizer
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import prog8.intermediate.*
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class TestIRPeepholeOpt: FunSpec({
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fun makeIRProgram(lines: List<IRCodeLine>): IRProgram {
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fun makeIRProgram(instructions: List<IRCodeLine>): IRProgram {
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val block = IRBlock("main", null, IRBlock.BlockAlignment.NONE, Position.DUMMY)
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val sub = IRSubroutine("main.start", emptyList(), null, Position.DUMMY)
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val chunk = IRCodeChunk(Position.DUMMY)
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for(line in lines)
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chunk += line
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for(instr in instructions)
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chunk += instr
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sub += chunk
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block += sub
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val target = VMTarget()
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@ -30,7 +30,7 @@ class TestIRPeepholeOpt: FunSpec({
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return prog
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}
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fun IRProgram.lines(): List<IRCodeLine> = this.blocks.flatMap { it.subroutines }.flatMap { it.chunks }.flatMap { it.lines }
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fun IRProgram.instructions(): List<IRCodeLine> = this.blocks.flatMap { it.subroutines }.flatMap { it.chunks }.flatMap { it.instructions }
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test("remove nops") {
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val irProg = makeIRProgram(listOf(
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@ -38,10 +38,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.NOP),
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IRInstruction(Opcode.NOP)
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))
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irProg.lines().size shouldBe 3
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irProg.instructions().size shouldBe 3
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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irProg.lines().size shouldBe 1
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irProg.instructions().size shouldBe 1
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}
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test("remove jmp to label below") {
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@ -55,10 +55,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=1),
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IRCodeLabel("label3")
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))
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irProg.lines().size shouldBe 8
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irProg.instructions().size shouldBe 8
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 5
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(lines[0] as IRCodeLabel).name shouldBe "label"
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(lines[1] as IRCodeLabel).name shouldBe "label2"
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@ -76,10 +76,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.CLC),
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IRInstruction(Opcode.CLC)
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))
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irProg.lines().size shouldBe 6
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irProg.instructions().size shouldBe 6
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 1
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(lines[0] as IRInstruction).opcode shouldBe Opcode.CLC
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}
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@ -91,10 +91,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.PUSH, IRDataType.BYTE, reg1=99),
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IRInstruction(Opcode.POP, IRDataType.BYTE, reg1=222)
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))
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irProg.lines().size shouldBe 4
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irProg.instructions().size shouldBe 4
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 1
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(lines[0] as IRInstruction).opcode shouldBe Opcode.LOADR
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(lines[0] as IRInstruction).reg1 shouldBe 222
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@ -114,10 +114,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.ADD, IRDataType.BYTE, reg1=42, value = 0),
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IRInstruction(Opcode.SUB, IRDataType.BYTE, reg1=42, value = 0)
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))
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irProg.lines().size shouldBe 10
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irProg.instructions().size shouldBe 10
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 4
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}
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@ -126,10 +126,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.ADD, IRDataType.BYTE, reg1=42, value = 1),
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IRInstruction(Opcode.SUB, IRDataType.BYTE, reg1=42, value = 1)
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))
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irProg.lines().size shouldBe 2
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irProg.instructions().size shouldBe 2
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 2
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(lines[0] as IRInstruction).opcode shouldBe Opcode.INC
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(lines[1] as IRInstruction).opcode shouldBe Opcode.DEC
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@ -146,10 +146,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.OR, IRDataType.BYTE, reg1=42, value = 1),
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IRInstruction(Opcode.XOR, IRDataType.BYTE, reg1=42, value = 1)
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))
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irProg.lines().size shouldBe 8
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irProg.instructions().size shouldBe 8
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 4
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}
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@ -160,10 +160,10 @@ class TestIRPeepholeOpt: FunSpec({
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IRInstruction(Opcode.OR, IRDataType.BYTE, reg1=42, value = 255),
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IRInstruction(Opcode.OR, IRDataType.WORD, reg1=42, value = 65535)
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))
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irProg.lines().size shouldBe 4
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irProg.instructions().size shouldBe 4
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val opt = IRPeepholeOptimizer(irProg)
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opt.optimize()
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val lines = irProg.lines()
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val lines = irProg.instructions()
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lines.size shouldBe 4
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(lines[0] as IRInstruction).opcode shouldBe Opcode.LOAD
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(lines[1] as IRInstruction).opcode shouldBe Opcode.LOAD
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@ -3,6 +3,9 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- ir: get rid of IRCodeLabel, make every label start a new code chunk, give those a 'label' property.
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- ir: fix joinChunks() in the IR optimizer ?
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...
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@ -19,8 +22,6 @@ Compiler:
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- create BSS section in output program and put StStaticVariables in there with bss=true. Don't forget to add init code to zero out everything that was put in bss. If array in bss->only zero ONCE! So requires self-modifying code
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- ir: Jumps go to a code block rather than a specific address(label) -> also helps future dead code elimination?
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- ir: the above means that every label introduces a new code block. This eliminates the use of actual labels altogether during execution/translation.
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- ir: joinChunks() in the IR optimizer should be changed accordingly
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- ir: add more optimizations in IRPeepholeOptimizer
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- ir: how to remove all unused subroutines? (the 6502 assembly codegen relies on 64tass solve this for us)
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- see if we can let for loops skip the loop if end<start, like other programming languages. Without adding a lot of code size/duplicating the loop condition.
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@ -11,7 +11,7 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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private val outfile = outfileOverride ?: (irProgram.options.outputDir / ("${irProgram.name}.p8ir"))
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private val out = outfile.bufferedWriter()
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private var numChunks = 0
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private var numLines = 0
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private var numInstr = 0
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fun write(): Path {
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@ -35,7 +35,7 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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val used = irProgram.registersUsed()
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val numberUsed = (used.inputRegs.keys + used.outputRegs.keys).size + (used.inputFpRegs.keys + used.outputFpRegs.keys).size
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println("($numLines lines in $numChunks code chunks, $numberUsed registers)")
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println("($numInstr instructions in $numChunks chunks, $numberUsed registers)")
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return outfile
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}
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@ -63,11 +63,11 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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is IRInlineBinaryChunk -> writeInlineBytes(chunk)
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else -> {
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out.write("<C>\n")
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if (chunk.lines.isEmpty())
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if (chunk.instructions.isEmpty())
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throw InternalCompilerException("empty code chunk in ${it.name} ${it.position}")
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chunk.lines.forEach { line ->
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numLines++
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out.writeLine(line)
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chunk.instructions.forEach { instr ->
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numInstr++
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out.writeLine(instr)
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}
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out.write("</C>\n")
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}
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@ -55,7 +55,7 @@ class IRProgram(val name: String,
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val globalInits = mutableListOf<IRCodeLine>()
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val blocks = mutableListOf<IRBlock>()
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fun addGlobalInits(chunk: IRCodeChunk) = globalInits.addAll(chunk.lines)
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fun addGlobalInits(chunk: IRCodeChunk) = globalInits.addAll(chunk.instructions)
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fun addBlock(block: IRBlock) {
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require(blocks.all { it.name != block.name}) { "duplicate block ${block.name} ${block.position}" }
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blocks.add(block)
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@ -68,11 +68,11 @@ class IRProgram(val name: String,
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fun validate() {
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blocks.forEach {
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it.inlineAssembly.forEach { chunk ->
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require(chunk.lines.isEmpty())
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require(chunk.instructions.isEmpty())
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}
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it.subroutines.forEach { sub ->
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sub.chunks.forEach { chunk ->
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if (chunk is IRInlineAsmChunk) { require(chunk.lines.isEmpty()) }
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if (chunk is IRInlineAsmChunk) { require(chunk.instructions.isEmpty()) }
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}
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}
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}
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@ -176,7 +176,7 @@ sealed class IRCodeLine
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class IRCodeLabel(val name: String): IRCodeLine()
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abstract class IRCodeChunkBase(val position: Position) {
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val lines = mutableListOf<IRCodeLine>()
|
||||
val instructions = mutableListOf<IRCodeLine>()
|
||||
|
||||
abstract fun isEmpty(): Boolean
|
||||
abstract fun isNotEmpty(): Boolean
|
||||
@ -185,14 +185,14 @@ abstract class IRCodeChunkBase(val position: Position) {
|
||||
|
||||
class IRCodeChunk(position: Position): IRCodeChunkBase(position) {
|
||||
|
||||
override fun isEmpty() = lines.isEmpty()
|
||||
override fun isNotEmpty() = lines.isNotEmpty()
|
||||
override fun isEmpty() = instructions.isEmpty()
|
||||
override fun isNotEmpty() = instructions.isNotEmpty()
|
||||
override fun usedRegisters(): RegistersUsed {
|
||||
val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
|
||||
val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
|
||||
val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
|
||||
val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
|
||||
lines.forEach {
|
||||
instructions.forEach {
|
||||
if(it is IRInstruction)
|
||||
it.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
|
||||
}
|
||||
@ -200,11 +200,11 @@ class IRCodeChunk(position: Position): IRCodeChunkBase(position) {
|
||||
}
|
||||
|
||||
operator fun plusAssign(line: IRCodeLine) {
|
||||
lines.add(line)
|
||||
instructions.add(line)
|
||||
}
|
||||
|
||||
operator fun plusAssign(chunk: IRCodeChunkBase) {
|
||||
lines.addAll(chunk.lines)
|
||||
instructions.addAll(chunk.instructions)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ class VmProgramLoader {
|
||||
when (chunk) {
|
||||
is IRInlineAsmChunk -> addAssemblyToProgram(chunk, program, symbolAddresses)
|
||||
is IRInlineBinaryChunk -> program += IRInstruction(Opcode.BINARYDATA, binaryData = chunk.data)
|
||||
else -> addToProgram(chunk.lines, program, symbolAddresses)
|
||||
else -> addToProgram(chunk.instructions, program, symbolAddresses)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -187,11 +187,11 @@ class VmProgramLoader {
|
||||
}
|
||||
|
||||
private fun addToProgram(
|
||||
lines: Iterable<IRCodeLine>,
|
||||
instructions: Iterable<IRCodeLine>,
|
||||
program: MutableList<IRInstruction>,
|
||||
symbolAddresses: MutableMap<String, Int>
|
||||
) {
|
||||
lines.map {
|
||||
instructions.map {
|
||||
when(it) {
|
||||
is IRInstruction -> {
|
||||
it.labelSymbol?.let { symbol -> placeholders[program.size]=symbol }
|
||||
|
||||
@ -61,8 +61,8 @@ class TestVm: FunSpec( {
|
||||
vm.memory.getUW(1000) shouldBe 12345u
|
||||
vm.callStack.shouldBeEmpty()
|
||||
vm.valueStack.shouldBeEmpty()
|
||||
vm.pc shouldBe code.lines.size-1
|
||||
vm.stepCount shouldBe code.lines.size
|
||||
vm.pc shouldBe code.instructions.size-1
|
||||
vm.stepCount shouldBe code.instructions.size
|
||||
}
|
||||
|
||||
test("vm asmsub not supported") {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user