diff --git a/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt b/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt
index 5e55590f6..cdc8c43dd 100644
--- a/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt
+++ b/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt
@@ -15,7 +15,7 @@ class C128MachineDefinition: IMachineDefinition {
     override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
     override val STARTUP_CODE_RESERVED_SIZE = 20u
     override val PROGRAM_LOAD_ADDRESS = 0x1c01u
-    override val PROGRAM_MEMTOP_ADDRESS = 0xff00u
+    override val PROGRAM_MEMTOP_ADDRESS = 0xc000u
 
     override val BSSHIGHRAM_START = 0u    // TODO
     override val BSSHIGHRAM_END = 0u      // TODO
diff --git a/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt b/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt
index 375f68333..d8a161490 100644
--- a/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt
+++ b/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt
@@ -20,7 +20,7 @@ class C64MachineDefinition: IMachineDefinition {
             // note that at $cfe0-$cfff are the 16 'virtual registers' R0-R15
 
     override val BSSHIGHRAM_START = 0xc000u
-    override val BSSHIGHRAM_END = 0xcfffu
+    override val BSSHIGHRAM_END = 0xcfdfu
     override val BSSGOLDENRAM_START = 0u
     override val BSSGOLDENRAM_END = 0u