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vm: add in-place bitwise or,and,xor
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parent
c9e8c7a290
commit
26ea1da146
@ -87,9 +87,9 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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"-" -> return expressionEval.operatorMinusInplace(address, vmDt, operand)
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"-" -> return expressionEval.operatorMinusInplace(address, vmDt, operand)
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"*" -> return expressionEval.operatorMultiplyInplace(address, vmDt, operand)
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"*" -> return expressionEval.operatorMultiplyInplace(address, vmDt, operand)
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"/" -> return expressionEval.operatorDivideInplace(address, vmDt, signed, operand)
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"/" -> return expressionEval.operatorDivideInplace(address, vmDt, signed, operand)
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"|" -> { /* TODO */ }
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"|" -> return expressionEval.operatorOrInplace(address, vmDt, operand)
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"&" -> { /* TODO */ }
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"&" -> return expressionEval.operatorAndInplace(address, vmDt, operand)
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"^" -> { /* TODO */ }
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"^" -> return expressionEval.operatorXorInplace(address, vmDt, operand)
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else -> {}
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else -> {}
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}
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}
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return fallbackAssign(origAssign)
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return fallbackAssign(origAssign)
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@ -477,6 +477,14 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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return code
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}
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}
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internal fun operatorXorInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.XORM, vmDt, reg1=operandReg, value = address)
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return code
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}
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private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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@ -486,6 +494,14 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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return code
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}
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}
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internal fun operatorAndInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.ANDM, vmDt, reg1=operandReg, value=address)
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return code
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}
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private fun operatorOr(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorOr(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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@ -495,6 +511,14 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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return code
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}
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}
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internal fun operatorOrInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.ORM, vmDt, reg1=operandReg, value = address)
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return code
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}
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private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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if(vmDt==VmDataType.FLOAT)
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if(vmDt==VmDataType.FLOAT)
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throw IllegalArgumentException("floating-point modulo not supported")
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throw IllegalArgumentException("floating-point modulo not supported")
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@ -3,7 +3,6 @@ TODO
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For next release
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For next release
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^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^
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- vm: implement the missing in-place operators in inplaceBinexpr()
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- complete the Inliner
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- complete the Inliner
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- add McCarthy evaluation to shortcircuit and/or expressions. First do ifs by splitting them up? Then do expressions that compute a value?
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- add McCarthy evaluation to shortcircuit and/or expressions. First do ifs by splitting them up? Then do expressions that compute a value?
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@ -27,6 +26,7 @@ Compiler:
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- vm: don't store symbol names in instructions to make optimizing the IR easier? but what about jumps to labels. And it's no longer readable by humans.
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- vm: don't store symbol names in instructions to make optimizing the IR easier? but what about jumps to labels. And it's no longer readable by humans.
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- vm: how to remove all unused subroutines? (in the assembly codegen, we let 64tass solve this for us)
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- vm: how to remove all unused subroutines? (in the assembly codegen, we let 64tass solve this for us)
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- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks' that have entry and exit points -> even better dead code elimination possible too
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- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks' that have entry and exit points -> even better dead code elimination possible too
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- vm: add more assignments to translateInplaceAssign()
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- when the vm is stable and *if* its language can get promoted to prog8 IL, the variable allocation should be changed.
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- when the vm is stable and *if* its language can get promoted to prog8 IL, the variable allocation should be changed.
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It's now done before the vm code generation, but the IL should probably not depend on the allocations already performed.
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It's now done before the vm code generation, but the IL should probably not depend on the allocations already performed.
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So the CodeGen doesn't do VariableAlloc *before* the codegen, but as a last step.
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So the CodeGen doesn't do VariableAlloc *before* the codegen, but as a last step.
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@ -1,51 +1,14 @@
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%import textio
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%import math
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%zeropage dontuse
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%zeropage dontuse
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; NOTE: meant to test to virtual machine output target (use -target vitual)
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; NOTE: meant to test to virtual machine output target (use -target vitual)
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main {
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main {
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sub start() {
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sub start() {
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byte @shared xx = 11
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ubyte @shared xx = 11
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byte @shared yy = 62
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uword addr = $5000
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byte @shared yy2 = 15
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@(addr) = @(addr) + xx
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byte @shared yy3 = 127
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xx = xx ^ 44
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ubyte @shared ubx = 3
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xx = xx | 44
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xx = xx & 44
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xx = xx + 9
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txt.print_b(xx) ; 20
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txt.nl()
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xx = xx * 8
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txt.print_b(xx) ; -96
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txt.nl()
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xx = xx - 7
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txt.print_b(xx) ; -103
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txt.nl()
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xx = xx / 6
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txt.print_b(xx) ; -17
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txt.nl()
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xx = xx * 5
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txt.print_b(xx) ; -85
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txt.nl()
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txt.nl()
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; xx = xx+3*yy
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; xx = xx/yy
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; xx = -xx
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; @($4000) = @($4000)
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; @($4000) = @($4000) + 2
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; xx = xx ^ yy
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; xx = xx | yy2
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; xx = xx & yy3
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; txt.print_b(xx) ; 63
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; txt.nl()
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; xx = (not xx) as byte
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; xx = (~xx) as byte
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; xx++
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; txt.print_b(xx) ; 0
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; txt.nl()
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;
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; ubx = not ubx
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; ubx = ~ubx
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}
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}
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}
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}
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@ -9,6 +9,7 @@ Virtual machine:
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65536 bytes of memory. Thus memory pointers (addresses) are limited to 16 bits.
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65536 bytes of memory. Thus memory pointers (addresses) are limited to 16 bits.
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Value stack, max 128 entries of 1 byte each.
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Value stack, max 128 entries of 1 byte each.
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Status registers: Carry, Zero, Negative.
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Status registers: Carry, Zero, Negative.
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Program to execute is not stored in this memory, it's just a separate list of instructions.
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Most instructions have an associated data type 'b','w','f'. (omitting it means 'b'/byte).
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Most instructions have an associated data type 'b','w','f'. (omitting it means 'b'/byte).
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Currently NO support for 24 or 32 bits integers.
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Currently NO support for 24 or 32 bits integers.
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@ -119,7 +120,9 @@ LOGICAL/BITWISE
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All have type b or w.
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All have type b or w.
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and reg1, reg2 - reg1 = reg1 bitwise and reg2
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and reg1, reg2 - reg1 = reg1 bitwise and reg2
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andm reg1 address - memory = memory bitwise and reg1
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or reg1, reg2 - reg1 = reg1 bitwise or reg2
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or reg1, reg2 - reg1 = reg1 bitwise or reg2
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orm reg1, address - memory = memory bitwise or reg1
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xor reg1, reg2 - reg1 = reg1 bitwise xor reg2
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xor reg1, reg2 - reg1 = reg1 bitwise xor reg2
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xorm reg1, address - memory = memory bitwise xor reg1
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xorm reg1, address - memory = memory bitwise xor reg1
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not reg1 - reg1 = boolean not of reg1 (0->1 , ~0 -> 0)
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not reg1 - reg1 = boolean not of reg1 (0->1 , ~0 -> 0)
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@ -240,7 +243,9 @@ enum class Opcode {
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EXTS,
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EXTS,
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AND,
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AND,
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ANDM,
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OR,
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OR,
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ORM,
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XOR,
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XOR,
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XORM,
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XORM,
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NOT,
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NOT,
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@ -303,7 +308,9 @@ val OpcodesWithAddress = setOf(
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Opcode.DIVM,
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Opcode.DIVM,
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Opcode.DIVSM,
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Opcode.DIVSM,
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Opcode.NOTM,
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Opcode.NOTM,
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Opcode.XORM
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Opcode.ORM,
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Opcode.XORM,
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Opcode.ANDM
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)
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)
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@ -509,7 +516,9 @@ val instructionFormats = mutableMapOf(
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Opcode.EXT to InstructionFormat.from("BW,r1"),
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Opcode.EXT to InstructionFormat.from("BW,r1"),
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Opcode.EXTS to InstructionFormat.from("BW,r1"),
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Opcode.EXTS to InstructionFormat.from("BW,r1"),
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Opcode.AND to InstructionFormat.from("BW,r1,r2"),
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Opcode.AND to InstructionFormat.from("BW,r1,r2"),
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Opcode.ANDM to InstructionFormat.from("BW,r1,v"),
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Opcode.OR to InstructionFormat.from("BW,r1,r2"),
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Opcode.OR to InstructionFormat.from("BW,r1,r2"),
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Opcode.ORM to InstructionFormat.from("BW,r1,v"),
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Opcode.XOR to InstructionFormat.from("BW,r1,r2"),
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Opcode.XOR to InstructionFormat.from("BW,r1,r2"),
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Opcode.XORM to InstructionFormat.from("BW,r1,v"),
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Opcode.XORM to InstructionFormat.from("BW,r1,v"),
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Opcode.NOT to InstructionFormat.from("BW,r1"),
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Opcode.NOT to InstructionFormat.from("BW,r1"),
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@ -155,7 +155,9 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.EXT -> InsEXT(ins)
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Opcode.EXT -> InsEXT(ins)
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Opcode.EXTS -> InsEXTS(ins)
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Opcode.EXTS -> InsEXTS(ins)
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Opcode.AND -> InsAND(ins)
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Opcode.AND -> InsAND(ins)
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Opcode.ANDM -> InsANDM(ins)
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Opcode.OR -> InsOR(ins)
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Opcode.OR -> InsOR(ins)
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Opcode.ORM -> InsORM(ins)
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Opcode.XOR -> InsXOR(ins)
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Opcode.XOR -> InsXOR(ins)
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Opcode.XORM ->InsXORM(ins)
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Opcode.XORM ->InsXORM(ins)
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Opcode.NOT -> InsNOT(ins)
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Opcode.NOT -> InsNOT(ins)
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@ -977,7 +979,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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"*" -> memvalue * operand
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"*" -> memvalue * operand
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else -> throw IllegalArgumentException("operator word $operator")
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else -> throw IllegalArgumentException("operator word $operator")
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}
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}
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registers.setUW(reg1, result.toUShort())
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memory.setUW(address, result.toUShort())
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}
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}
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private fun divModWordUnsigned(operator: String, reg1: Int, reg2: Int) {
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private fun divModWordUnsigned(operator: String, reg1: Int, reg2: Int) {
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@ -1091,6 +1093,16 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsANDM(i: Instruction) {
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val address = i.value!!
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when(i.type!!) {
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VmDataType.BYTE -> memory.setUB(address, (memory.getUB(address) and registers.getUB(i.reg1!!)))
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VmDataType.WORD -> memory.setUW(address, (memory.getUW(address) and registers.getUW(i.reg1!!)))
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VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
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}
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pc++
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}
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private fun InsOR(i: Instruction) {
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private fun InsOR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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when(i.type!!) {
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when(i.type!!) {
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@ -1101,6 +1113,16 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsORM(i: Instruction) {
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val address = i.value!!
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when(i.type!!) {
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VmDataType.BYTE -> memory.setUB(address, (memory.getUB(address) or registers.getUB(i.reg1!!)))
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VmDataType.WORD -> memory.setUW(address, (memory.getUW(address) or registers.getUW(i.reg1!!)))
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VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
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}
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pc++
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}
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private fun InsXOR(i: Instruction) {
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private fun InsXOR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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when(i.type!!) {
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when(i.type!!) {
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