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fix and optimize inplace invert and negate
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parent
78e84182f0
commit
2f756f1e3a
@ -289,20 +289,61 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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is PtPrefix -> {
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if(assign.target.array==null) {
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if(assign.source.datatype==assign.target.datatype) {
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// First assign the value to the target then apply the operator in place on the target.
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// This saves a temporary variable
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translateNormalAssignment(
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AsmAssignment(
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AsmAssignSource.fromAstSource(value.value, program, asmgen),
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assign.target, program.memsizer, assign.position
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), scope
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)
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when (value.operator) {
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"+" -> {}
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"-" -> inplaceNegate(assign, true, scope)
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"~" -> inplaceInvert(assign, scope)
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"not" -> throw AssemblyError("not should have been replaced in the Ast by ==0")
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else -> throw AssemblyError("invalid prefix operator")
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if(assign.source.datatype in IntegerDatatypes) {
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val signed = assign.source.datatype in SignedDatatypes
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if(assign.source.datatype in ByteDatatypes) {
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assignExpressionToRegister(value.value, RegisterOrPair.A, signed)
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when(value.operator) {
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"+" -> {}
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"-" -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" eor #255 | ina")
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else
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asmgen.out(" eor #255 | clc | adc #1")
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}
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"~" -> asmgen.out(" eor #255")
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"not" -> throw AssemblyError("not should have been replaced in the Ast by ==0")
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else -> throw AssemblyError("invalid prefix operator")
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}
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assignRegisterByte(assign.target, CpuRegister.A, signed)
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} else {
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assignExpressionToRegister(value.value, RegisterOrPair.AY, signed)
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when(value.operator) {
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"+" -> {}
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"-" -> {
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asmgen.out("""
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sec
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eor #255
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adc #0
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pha
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tya
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eor #255
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adc #0
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tay
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pla""")
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}
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"~" -> asmgen.out(" pha | tya | eor #255 | tay | pla | eor #255")
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"not" -> throw AssemblyError("not should have been replaced in the Ast by ==0")
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else -> throw AssemblyError("invalid prefix operator")
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}
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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}
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} else {
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// First assign the value to the target then apply the operator in place on the target.
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// This saves a temporary variable
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translateNormalAssignment(
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AsmAssignment(
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AsmAssignSource.fromAstSource(value.value, program, asmgen),
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assign.target, program.memsizer, assign.position
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), scope
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)
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when (value.operator) {
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"+" -> {}
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"-" -> inplaceNegate(assign, true, scope)
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"~" -> inplaceInvert(assign, scope)
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"not" -> throw AssemblyError("not should have been replaced in the Ast by ==0")
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else -> throw AssemblyError("invalid prefix operator")
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}
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}
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} else {
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// use a temporary variable
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@ -3657,11 +3698,18 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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DataType.BYTE -> {
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when (target.kind) {
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TargetStorageKind.VARIABLE -> {
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asmgen.out("""
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lda #0
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sec
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sbc ${target.asmVarname}
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sta ${target.asmVarname}""")
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out("""
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lda ${target.asmVarname}
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eor #255
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ina
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sta ${target.asmVarname}""")
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else
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asmgen.out("""
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lda #0
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sec
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sbc ${target.asmVarname}
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sta ${target.asmVarname}""")
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}
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TargetStorageKind.REGISTER -> {
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when(target.register!!) {
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@ -3670,7 +3718,6 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" eor #255 | ina")
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else
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asmgen.out(" eor #255 | clc | adc #1")
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}
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RegisterOrPair.X -> asmgen.out(" txa | eor #255 | tax | inx")
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RegisterOrPair.Y -> asmgen.out(" tya | eor #255 | tay | iny")
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