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optimize division by powers of 2 better (into bit shifts)
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@ -3,7 +3,7 @@ package prog8.code.core
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import kotlin.math.abs
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import kotlin.math.pow
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val powersOfTwoFloat = (1..16).map { (2.0).pow(it) }.toTypedArray()
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val powersOfTwoFloat = (0..16).map { (2.0).pow(it) }.toTypedArray()
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val negativePowersOfTwoFloat = powersOfTwoFloat.map { -it }.toTypedArray()
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val powersOfTwoInt = (0..16).map { 2.0.pow(it).toInt() }.toTypedArray()
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@ -933,11 +933,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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private fun optimizedDivideExpr(expr: PtBinaryExpression, target: AsmAssignTarget): Boolean {
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val constDivisor = expr.right.asConstInteger()
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if(constDivisor in powersOfTwoInt) {
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println("TODO optimize: divide ${expr.type} by power-of-2 ${constDivisor} at ${expr.position}") // TODO
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}
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// replacing division by shifting is done in an optimizer step.
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when(expr.type) {
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DataType.UBYTE -> {
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assignExpressionToRegister(expr.left, RegisterOrPair.A, false)
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@ -1477,9 +1477,7 @@ $shortcutLabel:""")
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asmgen.out(" lda $name | ldy #$value | jsr math.multiply_bytes | sta $name")
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}
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"/" -> {
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if(value in powersOfTwoInt) {
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println("TODO optimize: (u)byte division by power-of-2 $value") // TODO
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}
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// replacing division by shifting is done in an optimizer step.
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if (dt == DataType.UBYTE)
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asmgen.out(" lda $name | ldy #$value | jsr math.divmod_ub_asm | sty $name")
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else
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@ -1828,36 +1826,36 @@ $shortcutLabel:""")
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}
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}
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"/" -> {
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if(value==0)
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// replacing division by shifting is done in an optimizer step.
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if(value==0) {
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throw AssemblyError("division by zero")
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else if (value in powersOfTwoInt) {
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println("TODO optimize: (u)word division by power-of-2 $value") // TODO
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}
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if(dt==DataType.WORD) {
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asmgen.out("""
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_w_asm
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sta $lsb
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sty $msb
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""")
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}
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else {
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asmgen.out("""
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_uw_asm
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sta $lsb
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sty $msb
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""")
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} else {
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if(dt==DataType.WORD) {
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asmgen.out("""
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_w_asm
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sta $lsb
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sty $msb
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""")
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}
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else {
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asmgen.out("""
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_uw_asm
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sta $lsb
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sty $msb
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""")
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}
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}
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}
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"%" -> {
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@ -783,19 +783,31 @@ class IRCodeGen(
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if(factor==1)
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return code
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val pow2 = powersOfTwoInt.indexOf(factor)
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// TODO also try to optimize for signed division by powers of 2
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if(pow2==1 && !signed) {
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code += IRInstruction(Opcode.LSR, dt, reg1=reg) // simple single bit shift
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}
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else if(pow2>=1 &&!signed) {
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// just shift multiple bits (unsigned)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
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code += if(signed)
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IRInstruction(Opcode.ASRN, dt, reg1=reg, reg2=pow2reg)
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else
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IRInstruction(Opcode.LSRN, dt, reg1=reg, reg2=pow2reg)
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if(pow2>=0) {
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if(signed) {
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if(pow2==1) {
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// simple single bit shift (signed)
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code += IRInstruction(Opcode.ASR, dt, reg1=reg)
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} else {
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// just shift multiple bits (signed)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
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code += IRInstruction(Opcode.ASRN, dt, reg1=reg, reg2=pow2reg)
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}
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} else {
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if(pow2==1) {
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// simple single bit shift (unsigned)
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code += IRInstruction(Opcode.LSR, dt, reg1=reg)
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} else {
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// just shift multiple bits (unsigned)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1 = pow2reg, immediate = pow2)
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code += IRInstruction(Opcode.LSRN, dt, reg1 = reg, reg2 = pow2reg)
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}
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}
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return code
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} else {
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// regular div
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code += if (factor == 0) {
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IRInstruction(Opcode.LOAD, dt, reg1=reg, immediate = 0xffff)
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} else {
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@ -804,8 +816,8 @@ class IRCodeGen(
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else
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IRInstruction(Opcode.DIV, dt, reg1=reg, immediate = factor)
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}
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return code
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}
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return code
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}
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internal fun divideByConstInplace(dt: IRDataType, knownAddress: Int?, symbol: String?, factor: Int, signed: Boolean): IRCodeChunk {
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@ -813,31 +825,47 @@ class IRCodeGen(
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if(factor==1)
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return code
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val pow2 = powersOfTwoInt.indexOf(factor)
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// TODO also try to optimize for signed division by powers of 2
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if(pow2==1 && !signed) {
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// just simple bit shift
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code += if(knownAddress!=null)
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IRInstruction(Opcode.LSRM, dt, address = knownAddress)
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else
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IRInstruction(Opcode.LSRM, dt, labelSymbol = symbol)
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if(pow2>=0) {
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// can do bit shift instead of division
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if(signed) {
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if(pow2==1) {
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// just simple bit shift (signed)
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code += if (knownAddress != null)
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IRInstruction(Opcode.ASRM, dt, address = knownAddress)
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else
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IRInstruction(Opcode.ASRM, dt, labelSymbol = symbol)
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} else {
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// just shift multiple bits (signed)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1 = pow2reg, immediate = pow2)
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code += if (knownAddress != null)
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IRInstruction(Opcode.ASRNM, dt, reg1 = pow2reg, address = knownAddress)
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else
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IRInstruction(Opcode.ASRNM, dt, reg1 = pow2reg, labelSymbol = symbol)
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}
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} else {
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if(pow2==1) {
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// just simple bit shift (unsigned)
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code += if(knownAddress!=null)
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IRInstruction(Opcode.LSRM, dt, address = knownAddress)
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else
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IRInstruction(Opcode.LSRM, dt, labelSymbol = symbol)
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}
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else {
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// just shift multiple bits (unsigned)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
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code += if(knownAddress!=null)
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IRInstruction(Opcode.LSRNM, dt, reg1 = pow2reg, address = knownAddress)
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else
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IRInstruction(Opcode.LSRNM, dt, reg1 = pow2reg, labelSymbol = symbol)
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}
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}
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return code
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}
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else if(pow2>=1 && !signed) {
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// just shift multiple bits (unsigned)
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val pow2reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
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code += if(signed) {
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if(knownAddress!=null)
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IRInstruction(Opcode.ASRNM, dt, reg1 = pow2reg, address = knownAddress)
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else
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IRInstruction(Opcode.ASRNM, dt, reg1 = pow2reg, labelSymbol = symbol)
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}
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else {
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if(knownAddress!=null)
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IRInstruction(Opcode.LSRNM, dt, reg1 = pow2reg, address = knownAddress)
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else
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IRInstruction(Opcode.LSRNM, dt, reg1 = pow2reg, labelSymbol = symbol)
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}
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} else {
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else
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{
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// regular div
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if (factor == 0) {
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val reg = registers.nextFree()
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code += IRInstruction(Opcode.LOAD, dt, reg1=reg, immediate = 0xffff)
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@ -862,8 +890,8 @@ class IRCodeGen(
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IRInstruction(Opcode.DIVM, dt, reg1 = factorReg, labelSymbol = symbol)
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}
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}
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return code
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}
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return code
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}
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private fun translate(ifElse: PtIfElse): IRCodeChunks {
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@ -708,6 +708,7 @@ class ExpressionSimplifier(private val program: Program, private val options: Co
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return null
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val leftDt = leftIDt.getOr(DataType.UNDEFINED)
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when (cv) {
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0.0 -> return null // fall through to regular float division to properly deal with division by zero
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-1.0 -> {
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// '/' -> -left
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if (expr.operator == "/") {
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@ -736,14 +737,10 @@ class ExpressionSimplifier(private val program: Program, private val options: Co
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}
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}
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in powersOfTwoFloat -> {
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if (leftDt==DataType.UBYTE || leftDt==DataType.UWORD) {
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// Unsigned number divided by a power of two => shift right
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// Signed number can't simply be bitshifted in this case (due to rounding issues for negative values),
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// so we leave that as is and let the code generator deal with it.
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val numshifts = log2(cv).toInt()
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val numshifts = powersOfTwoFloat.indexOf(cv)
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if (leftDt in IntegerDatatypes) {
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// division by a power of two => shift right (signed and unsigned)
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return BinaryExpression(expr.left, ">>", NumericLiteral.optimalInteger(numshifts, expr.position), expr.position)
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} else {
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println("TODO optimize: divide by power-of-2 $cv at ${expr.position}") // TODO
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}
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}
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}
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@ -5,11 +5,7 @@ See open issues on github.
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Re-generate the skeletons doc files.
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optimize byte/word division by powers of 2 (and shift right?), it's now often still using divmod routine. (also % ?)
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see the TODOs in inplacemodificationByteVariableWithLiteralval(), inplacemodificationSomeWordWithLiteralval(), optimizedDivideExpr(),
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and finally in optimizeDivision()
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and for IR: see divideByConst() / divideByConstInplace() in IRCodeGen
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optimize signed word bit shifting?:
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1 shift right of AX signed word:
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stx P8ZP_SCRATCH_B1
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cpx #$80
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}
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sub unsigned() {
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txt.print("unsigned\n")
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txt.print("\nunsigned\n")
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ubyte @shared ubvalue = 88
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uword @shared uwvalue = 8888
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