Merge branch 'better-ir'

This commit is contained in:
Irmen de Jong 2024-12-24 12:12:08 +01:00
commit 3850e1dbb5
8 changed files with 28 additions and 21 deletions

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@ -90,7 +90,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
return bittestCall
}
fun isAndByteCondition(condition: PtBinaryExpression?): Triple<PtBinaryExpression, PtIdentifier, Int>? {
fun isAndByteConditionForBRK(condition: PtBinaryExpression?): Triple<PtBinaryExpression, PtIdentifier, Int>? {
if(condition!=null && (condition.operator=="==" || condition.operator=="!=")) {
if (condition.right.asConstInteger() == 0) {
val and = condition.left as? PtBinaryExpression
@ -119,7 +119,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
walkAst(program) { node: PtNode, depth: Int ->
if(node is PtIfElse) {
val condition = node.condition as? PtBinaryExpression
val check = isAndByteCondition(condition)
val check = isAndByteConditionForBRK(condition)
if(check!=null) {
val (and, variable, bitmask) = check
val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)
@ -137,7 +137,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
}
if (node is PtIfExpression) {
val condition = node.condition as? PtBinaryExpression
val check = isAndByteCondition(condition)
val check = isAndByteConditionForBRK(condition)
if(check!=null) {
val (and, variable, bitmask) = check
val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)

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@ -1348,7 +1348,7 @@ class IRCodeGen(
val condition = ifElse.condition as? PtBinaryExpression
if(condition==null || !condition.left.type.isFloat) {
return ifWithElse_IntegerCond(ifElse)
return ifElse_IntegerCond(ifElse)
}
// we assume only a binary expression can contain a floating point.
@ -1408,7 +1408,7 @@ class IRCodeGen(
return result
}
private fun ifWithElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
private fun ifElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
val result = mutableListOf<IRCodeChunkBase>()
fun translateSimple(condition: PtExpression, jumpFalseOpcode: Opcode, addCmpiZero: Boolean) {

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@ -233,8 +233,8 @@ sys {
cx16 {
; the sixteen virtual 16-bit registers that the CX16 has defined in the zeropage
; they are simulated on the VirtualMachine as well but their location in memory is different
; the sixteen virtual 16-bit registers that the Commander X16 has defined in the zeropage
; they are on the VirtualMachine as well, but their location in memory is different
&uword r0 = $ff02
&uword r1 = $ff04
&uword r2 = $ff06

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@ -13,6 +13,7 @@ Future Things and Ideas
- Kotlin: can we use inline value classes in certain spots?
- Improve the SublimeText syntax file for prog8, you can also install this for 'bat': https://github.com/sharkdp/bat?tab=readme-ov-file#adding-new-syntaxes--language-definitions
- don't do BIT instruction tests via makeBittestCall() fake builtin function. Just do it in the code generator when it encounters the correct bitwise and sequence. (also IR)
- Compiling Libraries: improve ability to create library files in prog8; for instance there's still stuff injected into the start of the start() routine AND there is separate setup logic going on before calling it.
Make up our mind! Maybe all setup does need to be put into start() ? because the program cannot function correctly when the variables aren't initialized properly bss is not cleared etc. etc.
Add a -library $xxxx command line option (and/or some directive) to preselect every setting that is required to make a library at $xxxx rather than a normal loadable and runnable program?
@ -46,9 +47,6 @@ Future Things and Ideas
IR/VM
-----
- cx16.r0-r15 should not be translated to their (fake) addresses but remain symbolical, so they can be translated to what the actual target system specifies for them.
- prefix immediate values with '#' for readability reasons (no technical reason)
- ExpressionCodeResult: get rid of the separation between single result register and multiple result registers?
- implement missing operators in AssignmentGen (array shifts etc)
- support %align on code chunks
- fix call() return value handling
@ -65,6 +63,7 @@ IR/VM
- getting it in shape for code generation...
- make optimizeBitTest work for IR too to use the BIT instruction?
- make sure that a 6502 codegen based off the IR, still generates BIT instructions when testing bit 7 or 6 of a byte var.
- ExpressionCodeResult: get rid of the separation between single result register and multiple result registers? maybe not, this requires hundreds of lines to change
Libraries

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@ -1,14 +1,22 @@
%import textio
%zeropage basicsafe
%option no_sysinit
main {
sub start() {
const ubyte CVALUE = 123
const long CLONG = 555555
ubyte @shared vvalue = 99
&ubyte mmvar = $2000
cx16.r0L = CVALUE + 100
cx16.r1L = vvalue + 100
txt.print_ub(@($2000))
txt.nl()
@($2000) = 123
txt.print_ub(@($2000))
txt.nl()
mmvar = 42
txt.print_ub(@($2000))
txt.nl()
cx16.r0 = 123
}
}

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@ -1106,11 +1106,11 @@ data class IRInstruction(
result.add(",")
}
immediate?.let {
result.add(it.toHex())
result.add("#${it.toHex()}")
result.add(",")
}
immediateFp?.let {
result.add(it.toString())
result.add("#${it}")
result.add(",")
}
address?.let {

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@ -137,8 +137,8 @@ fun parseIRCodeLine(line: String): Either<IRInstruction, String> {
if (fpReg1 == null) fpReg1 = oper.substring(2).toInt()
else if (fpReg2 == null) fpReg2 = oper.substring(2).toInt()
else throw IRParseException("too many fp register operands")
} else if (oper[0].isDigit() || oper[0] == '$' || oper[0] == '%' || oper[0] == '-' || oper.startsWith("0x")) {
val value = parseIRValue(oper)
} else if (oper[0] in "0123456789$%-#" || oper.startsWith("0x")) {
val value = if(oper[0]=='#') parseIRValue(oper.drop(1)) else parseIRValue(oper)
if (format.immediate) {
if (immediateInt == null && immediateFp == null) {
if (type == IRDataType.FLOAT)

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@ -34,7 +34,7 @@ class TestInstructions: FunSpec({
ins.immediate shouldBe 0
ins.immediateFp shouldBe null
ins.labelSymbol shouldBe null
ins.toString() shouldBe "add.b r42,0,$63"
ins.toString() shouldBe "add.b r42,#0,$63"
}
test("with label") {
@ -49,7 +49,7 @@ class TestInstructions: FunSpec({
ins.immediate shouldBe 0
ins.immediateFp shouldBe null
ins.labelSymbol shouldBe "a.b.c"
ins.toString() shouldBe "add.w r11,0,a.b.c"
ins.toString() shouldBe "add.w r11,#0,a.b.c"
}
test("with output registers") {