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Merge branch 'better-ir'
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commit
3850e1dbb5
@ -90,7 +90,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
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return bittestCall
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}
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fun isAndByteCondition(condition: PtBinaryExpression?): Triple<PtBinaryExpression, PtIdentifier, Int>? {
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fun isAndByteConditionForBRK(condition: PtBinaryExpression?): Triple<PtBinaryExpression, PtIdentifier, Int>? {
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if(condition!=null && (condition.operator=="==" || condition.operator=="!=")) {
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if (condition.right.asConstInteger() == 0) {
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val and = condition.left as? PtBinaryExpression
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@ -119,7 +119,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
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walkAst(program) { node: PtNode, depth: Int ->
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if(node is PtIfElse) {
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val condition = node.condition as? PtBinaryExpression
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val check = isAndByteCondition(condition)
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val check = isAndByteConditionForBRK(condition)
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if(check!=null) {
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val (and, variable, bitmask) = check
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val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)
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@ -137,7 +137,7 @@ private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): In
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}
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if (node is PtIfExpression) {
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val condition = node.condition as? PtBinaryExpression
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val check = isAndByteCondition(condition)
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val check = isAndByteConditionForBRK(condition)
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if(check!=null) {
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val (and, variable, bitmask) = check
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val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)
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@ -1348,7 +1348,7 @@ class IRCodeGen(
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val condition = ifElse.condition as? PtBinaryExpression
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if(condition==null || !condition.left.type.isFloat) {
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return ifWithElse_IntegerCond(ifElse)
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return ifElse_IntegerCond(ifElse)
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}
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// we assume only a binary expression can contain a floating point.
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@ -1408,7 +1408,7 @@ class IRCodeGen(
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return result
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}
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private fun ifWithElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
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private fun ifElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
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val result = mutableListOf<IRCodeChunkBase>()
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fun translateSimple(condition: PtExpression, jumpFalseOpcode: Opcode, addCmpiZero: Boolean) {
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@ -233,8 +233,8 @@ sys {
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cx16 {
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; the sixteen virtual 16-bit registers that the CX16 has defined in the zeropage
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; they are simulated on the VirtualMachine as well but their location in memory is different
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; the sixteen virtual 16-bit registers that the Commander X16 has defined in the zeropage
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; they are on the VirtualMachine as well, but their location in memory is different
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&uword r0 = $ff02
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&uword r1 = $ff04
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&uword r2 = $ff06
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@ -13,6 +13,7 @@ Future Things and Ideas
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- Kotlin: can we use inline value classes in certain spots?
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- Improve the SublimeText syntax file for prog8, you can also install this for 'bat': https://github.com/sharkdp/bat?tab=readme-ov-file#adding-new-syntaxes--language-definitions
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- don't do BIT instruction tests via makeBittestCall() fake builtin function. Just do it in the code generator when it encounters the correct bitwise and sequence. (also IR)
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- Compiling Libraries: improve ability to create library files in prog8; for instance there's still stuff injected into the start of the start() routine AND there is separate setup logic going on before calling it.
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Make up our mind! Maybe all setup does need to be put into start() ? because the program cannot function correctly when the variables aren't initialized properly bss is not cleared etc. etc.
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Add a -library $xxxx command line option (and/or some directive) to preselect every setting that is required to make a library at $xxxx rather than a normal loadable and runnable program?
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@ -46,9 +47,6 @@ Future Things and Ideas
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IR/VM
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-----
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- cx16.r0-r15 should not be translated to their (fake) addresses but remain symbolical, so they can be translated to what the actual target system specifies for them.
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- prefix immediate values with '#' for readability reasons (no technical reason)
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- ExpressionCodeResult: get rid of the separation between single result register and multiple result registers?
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- implement missing operators in AssignmentGen (array shifts etc)
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- support %align on code chunks
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- fix call() return value handling
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@ -65,6 +63,7 @@ IR/VM
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- getting it in shape for code generation...
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- make optimizeBitTest work for IR too to use the BIT instruction?
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- make sure that a 6502 codegen based off the IR, still generates BIT instructions when testing bit 7 or 6 of a byte var.
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- ExpressionCodeResult: get rid of the separation between single result register and multiple result registers? maybe not, this requires hundreds of lines to change
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Libraries
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@ -1,14 +1,22 @@
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%import textio
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%zeropage basicsafe
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%option no_sysinit
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main {
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sub start() {
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const ubyte CVALUE = 123
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const long CLONG = 555555
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ubyte @shared vvalue = 99
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&ubyte mmvar = $2000
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cx16.r0L = CVALUE + 100
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cx16.r1L = vvalue + 100
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txt.print_ub(@($2000))
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txt.nl()
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@($2000) = 123
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txt.print_ub(@($2000))
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txt.nl()
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mmvar = 42
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txt.print_ub(@($2000))
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txt.nl()
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cx16.r0 = 123
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}
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}
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@ -1106,11 +1106,11 @@ data class IRInstruction(
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result.add(",")
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}
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immediate?.let {
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result.add(it.toHex())
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result.add("#${it.toHex()}")
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result.add(",")
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}
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immediateFp?.let {
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result.add(it.toString())
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result.add("#${it}")
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result.add(",")
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}
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address?.let {
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@ -137,8 +137,8 @@ fun parseIRCodeLine(line: String): Either<IRInstruction, String> {
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if (fpReg1 == null) fpReg1 = oper.substring(2).toInt()
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else if (fpReg2 == null) fpReg2 = oper.substring(2).toInt()
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else throw IRParseException("too many fp register operands")
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} else if (oper[0].isDigit() || oper[0] == '$' || oper[0] == '%' || oper[0] == '-' || oper.startsWith("0x")) {
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val value = parseIRValue(oper)
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} else if (oper[0] in "0123456789$%-#" || oper.startsWith("0x")) {
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val value = if(oper[0]=='#') parseIRValue(oper.drop(1)) else parseIRValue(oper)
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if (format.immediate) {
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if (immediateInt == null && immediateFp == null) {
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if (type == IRDataType.FLOAT)
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@ -34,7 +34,7 @@ class TestInstructions: FunSpec({
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ins.immediate shouldBe 0
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ins.immediateFp shouldBe null
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ins.labelSymbol shouldBe null
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ins.toString() shouldBe "add.b r42,0,$63"
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ins.toString() shouldBe "add.b r42,#0,$63"
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}
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test("with label") {
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@ -49,7 +49,7 @@ class TestInstructions: FunSpec({
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ins.immediate shouldBe 0
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ins.immediateFp shouldBe null
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ins.labelSymbol shouldBe "a.b.c"
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ins.toString() shouldBe "add.w r11,0,a.b.c"
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ins.toString() shouldBe "add.w r11,#0,a.b.c"
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}
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test("with output registers") {
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