mirror of
https://github.com/irmen/prog8.git
synced 2024-12-23 09:32:43 +00:00
added optimizer for IR code
with two very simple optimizations
This commit is contained in:
Irmen de Jong
parent
dc32318cec
commit
39132327cc
@ -7,6 +7,7 @@ import prog8.code.SymbolTable
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.intermediate.*
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import prog8.iroptimizer.IROptimizer
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import kotlin.io.path.readBytes
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import kotlin.math.pow
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@ -66,6 +67,11 @@ class IRCodeGen(
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irProg.linkChunks() // re-link
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}
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if(options.optimize) {
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val opt = IROptimizer(irProg)
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opt.optimize()
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}
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irProg.validate()
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return irProg
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}
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@ -217,7 +223,7 @@ class IRCodeGen(
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}
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program.allBlocks().forEach { block ->
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block.children.forEach {
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block.children.toList().forEach {
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if (it is PtSub) {
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// Only regular subroutines can have nested subroutines.
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it.children.filterIsInstance<PtSub>().forEach { subsub -> moveToBlock(block, it, subsub) }
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62
codeGenIntermediate/src/prog8/iroptimizer/IROptimizer.kt
Normal file
62
codeGenIntermediate/src/prog8/iroptimizer/IROptimizer.kt
Normal file
@ -0,0 +1,62 @@
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package prog8.iroptimizer
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import prog8.intermediate.*
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internal class IROptimizer(val program: IRProgram) {
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fun optimize() {
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program.blocks.forEach { block ->
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block.children.forEach { elt ->
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process(elt)
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}
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}
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}
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private fun process(elt: IIRBlockElement) {
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when(elt) {
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is IRCodeChunkBase -> {
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optimizeInstructions(elt)
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// TODO renumber registers that are only used within the code chunk
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// val used = elt.usedRegisters()
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}
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is IRAsmSubroutine -> {
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if(elt.asmChunk.isIR) {
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optimizeInstructions(elt.asmChunk)
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}
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// TODO renumber registers that are only used within the code chunk
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// val used = elt.usedRegisters()
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}
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is IRSubroutine -> {
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elt.chunks.forEach { process(it) }
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}
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}
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}
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private fun optimizeInstructions(elt: IRCodeChunkBase) {
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elt.instructions.withIndex().windowed(2).forEach {(first, second) ->
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val i1 = first.value
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val i2 = second.value
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// replace call + return --> jump
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if(i1.opcode==Opcode.CALL && i2.opcode==Opcode.RETURN) {
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elt.instructions[first.index] = IRInstruction(Opcode.JUMP, value=i1.value, labelSymbol = i1.labelSymbol, branchTarget = i1.branchTarget)
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elt.instructions[second.index] = IRInstruction(Opcode.NOP)
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if(second.index==elt.instructions.size-1) {
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// it was the last instruction, so the link to the next chunk needs to be cleared
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elt.next = null
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}
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}
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// replace subsequent opcodes that jump by just the first
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if(i1.opcode in OpcodesThatJump && i2.opcode in OpcodesThatJump) {
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elt.instructions[second.index] = IRInstruction(Opcode.NOP)
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}
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}
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// remove nops
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elt.instructions.withIndex()
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.filter { it.value.opcode==Opcode.NOP }
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.reversed()
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.forEach {
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elt.instructions.removeAt(it.index)
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}
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}
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}
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@ -3,6 +3,10 @@ TODO
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For next minor release
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^^^^^^^^^^^^^^^^^^^^^^
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- IR: don't hardcode r0/fr0 as return registers.
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instead have RETURN -> returns void, RETURNREG <register> -> return value from given register
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also CALL -> void call, CALLRVAL -> specify register to put call result in. CALLRVAL r0, functionThatReturnsInt
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...
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@ -39,7 +39,7 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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out.close()
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val used = irProgram.registersUsed()
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val numberUsed = (used.inputRegs.keys + used.outputRegs.keys).size + (used.inputFpRegs.keys + used.outputFpRegs.keys).size
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val numberUsed = (used.readRegs.keys + used.writeRegs.keys).size + (used.readFpRegs.keys + used.writeFpRegs.keys).size
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println("($numInstr instructions in $numChunks chunks, $numberUsed registers)")
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return outfile
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}
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@ -465,9 +465,9 @@ enum class IRDataType {
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enum class OperandDirection {
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UNUSED,
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INPUT,
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OUTPUT,
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INOUT
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READ,
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WRITE,
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READWRITE
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}
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data class InstructionFormat(val datatype: IRDataType?,
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@ -492,14 +492,14 @@ data class InstructionFormat(val datatype: IRDataType?,
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val typespec = splits.next()
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while(splits.hasNext()) {
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when(splits.next()) {
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"<r1" -> { reg1=OperandDirection.INPUT }
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">r1" -> { reg1=OperandDirection.OUTPUT }
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"<>r1" -> { reg1=OperandDirection.INOUT }
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"<r2" -> reg2 = OperandDirection.INPUT
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"<fr1" -> { fpreg1=OperandDirection.INPUT }
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">fr1" -> { fpreg1=OperandDirection.OUTPUT }
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"<>fr1" -> { fpreg1=OperandDirection.INOUT }
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"<fr2" -> fpreg2 = OperandDirection.INPUT
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"<r1" -> { reg1=OperandDirection.READ }
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">r1" -> { reg1=OperandDirection.WRITE }
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"<>r1" -> { reg1=OperandDirection.READWRITE }
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"<r2" -> reg2 = OperandDirection.READ
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"<fr1" -> { fpreg1=OperandDirection.READ }
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">fr1" -> { fpreg1=OperandDirection.WRITE }
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"<>fr1" -> { fpreg1=OperandDirection.READWRITE }
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"<fr2" -> fpreg2 = OperandDirection.READ
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"<v" -> {
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if('F' in typespec)
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fpvalueIn = true
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@ -524,9 +524,9 @@ data class InstructionFormat(val datatype: IRDataType?,
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}
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/*
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<X = X is not modified (input/readonly value)
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>X = X is overwritten with output value (output value)
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<>X = X is modified (read as input + written as output)
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<X = X is not modified (readonly value)
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>X = X is overwritten with output value (write value)
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<>X = X is modified (read + written)
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TODO: also encode if *memory* is read/written/modified?
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*/
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@Suppress("BooleanLiteralArgument")
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@ -755,38 +755,38 @@ data class IRInstruction(
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}
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fun addUsedRegistersCounts(
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inputRegs: MutableMap<Int, Int>,
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outputRegs: MutableMap<Int, Int>,
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inputFpRegs: MutableMap<Int, Int>,
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outputFpRegs: MutableMap<Int, Int>
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readRegs: MutableMap<Int, Int>,
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writeRegs: MutableMap<Int, Int>,
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readFpRegs: MutableMap<Int, Int>,
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writeFpRegs: MutableMap<Int, Int>
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) {
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when (this.reg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputRegs[this.reg1!!] = inputRegs.getValue(this.reg1)+1
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OperandDirection.OUTPUT -> outputRegs[this.reg1!!] = outputRegs.getValue(this.reg1)+1
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OperandDirection.INOUT -> {
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inputRegs[this.reg1!!] = inputRegs.getValue(this.reg1)+1
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outputRegs[this.reg1] = outputRegs.getValue(this.reg1)+1
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OperandDirection.READ -> readRegs[this.reg1!!] = readRegs.getValue(this.reg1)+1
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OperandDirection.WRITE -> writeRegs[this.reg1!!] = writeRegs.getValue(this.reg1)+1
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OperandDirection.READWRITE -> {
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readRegs[this.reg1!!] = readRegs.getValue(this.reg1)+1
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writeRegs[this.reg1] = writeRegs.getValue(this.reg1)+1
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}
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}
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when (this.reg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> outputRegs[this.reg2!!] = outputRegs.getValue(this.reg2)+1
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else -> throw IllegalArgumentException("reg2 can only be input")
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OperandDirection.READ -> writeRegs[this.reg2!!] = writeRegs.getValue(this.reg2)+1
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else -> throw IllegalArgumentException("reg2 can only be read")
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}
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when (this.fpReg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs[this.fpReg1!!] = inputFpRegs.getValue(this.fpReg1)+1
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OperandDirection.OUTPUT -> outputFpRegs[this.fpReg1!!] = outputFpRegs.getValue(this.fpReg1)+1
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OperandDirection.INOUT -> {
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inputFpRegs[this.fpReg1!!] = inputFpRegs.getValue(this.fpReg1)+1
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outputFpRegs[this.fpReg1] = outputFpRegs.getValue(this.fpReg1)+1
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OperandDirection.READ -> readFpRegs[this.fpReg1!!] = readFpRegs.getValue(this.fpReg1)+1
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OperandDirection.WRITE -> writeFpRegs[this.fpReg1!!] = writeFpRegs.getValue(this.fpReg1)+1
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OperandDirection.READWRITE -> {
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readFpRegs[this.fpReg1!!] = readFpRegs.getValue(this.fpReg1)+1
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writeFpRegs[this.fpReg1] = writeFpRegs.getValue(this.fpReg1)+1
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}
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}
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when (this.fpReg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs[this.fpReg2!!] = inputFpRegs.getValue(this.fpReg2)+1
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else -> throw IllegalArgumentException("fpReg2 can only be input")
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OperandDirection.READ -> readFpRegs[this.fpReg2!!] = readFpRegs.getValue(this.fpReg2)+1
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else -> throw IllegalArgumentException("fpReg2 can only be read")
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}
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}
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@ -199,19 +199,19 @@ class IRProgram(val name: String,
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}
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fun registersUsed(): RegistersUsed {
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val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val readRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val readFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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fun addUsed(usedRegisters: RegistersUsed) {
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usedRegisters.inputRegs.forEach{ (reg, count) -> inputRegs[reg] = inputRegs.getValue(reg) + count }
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usedRegisters.outputRegs.forEach{ (reg, count) -> outputRegs[reg] = outputRegs.getValue(reg) + count }
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usedRegisters.inputFpRegs.forEach{ (reg, count) -> inputFpRegs[reg] = inputFpRegs.getValue(reg) + count }
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usedRegisters.outputFpRegs.forEach{ (reg, count) -> outputFpRegs[reg] = outputFpRegs.getValue(reg) + count }
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usedRegisters.readRegs.forEach{ (reg, count) -> readRegs[reg] = readRegs.getValue(reg) + count }
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usedRegisters.writeRegs.forEach{ (reg, count) -> writeRegs[reg] = writeRegs.getValue(reg) + count }
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usedRegisters.readFpRegs.forEach{ (reg, count) -> readFpRegs[reg] = readFpRegs.getValue(reg) + count }
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usedRegisters.writeFpRegs.forEach{ (reg, count) -> writeFpRegs[reg] = writeFpRegs.getValue(reg) + count }
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}
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globalInits.instructions.forEach { it.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs) }
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globalInits.instructions.forEach { it.addUsedRegistersCounts(readRegs, writeRegs, readFpRegs, writeFpRegs) }
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blocks.forEach {block ->
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block.children.forEach { child ->
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when(child) {
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@ -224,7 +224,7 @@ class IRProgram(val name: String,
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}
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}
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return RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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return RegistersUsed(readRegs, writeRegs, readFpRegs, writeFpRegs)
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}
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}
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@ -333,12 +333,12 @@ class IRCodeChunk(label: String?, next: IRCodeChunkBase?): IRCodeChunkBase(label
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override fun isEmpty() = instructions.isEmpty()
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override fun isNotEmpty() = instructions.isNotEmpty()
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override fun usedRegisters(): RegistersUsed {
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val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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instructions.forEach { it.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs) }
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return RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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val readRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val readFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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instructions.forEach { it.addUsedRegistersCounts(readRegs, writeRegs, readFpRegs, writeFpRegs) }
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return RegistersUsed(readRegs, writeRegs, readFpRegs, writeFpRegs)
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}
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operator fun plusAssign(ins: IRInstruction) {
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@ -380,34 +380,34 @@ typealias IRCodeChunks = List<IRCodeChunkBase>
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class RegistersUsed(
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// register num -> number of uses
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val inputRegs: Map<Int, Int>,
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val outputRegs: Map<Int, Int>,
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val inputFpRegs: Map<Int, Int>,
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val outputFpRegs: Map<Int, Int>,
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val readRegs: Map<Int, Int>,
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val writeRegs: Map<Int, Int>,
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val readFpRegs: Map<Int, Int>,
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val writeFpRegs: Map<Int, Int>,
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) {
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override fun toString(): String {
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return "input=$inputRegs, output=$outputRegs, inputFp=$inputFpRegs, outputFp=$outputFpRegs"
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return "read=$readRegs, write=$writeRegs, readFp=$readFpRegs, writeFp=$writeFpRegs"
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}
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fun isEmpty() = inputRegs.isEmpty() && outputRegs.isEmpty() && inputFpRegs.isEmpty() && outputFpRegs.isEmpty()
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fun isEmpty() = readRegs.isEmpty() && writeRegs.isEmpty() && readFpRegs.isEmpty() && writeFpRegs.isEmpty()
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fun isNotEmpty() = !isEmpty()
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}
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private fun registersUsedInAssembly(isIR: Boolean, assembly: String): RegistersUsed {
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val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val readRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val readFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val writeFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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if(isIR) {
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assembly.lineSequence().forEach { line ->
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val result = parseIRCodeLine(line.trim(), null, mutableMapOf())
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result.fold(
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ifLeft = { it.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs) },
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ifLeft = { it.addUsedRegistersCounts(readRegs, writeRegs, readFpRegs, writeFpRegs) },
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ifRight = { /* labels can be skipped */ }
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)
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}
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}
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return RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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return RegistersUsed(readRegs, writeRegs, readFpRegs, writeFpRegs)
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}
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@ -24,7 +24,7 @@ class TestInstructions: FunSpec({
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val ins = IRInstruction(Opcode.BZ, IRDataType.BYTE, reg1=42, value = 99)
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ins.opcode shouldBe Opcode.BZ
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ins.type shouldBe IRDataType.BYTE
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ins.reg1direction shouldBe OperandDirection.INPUT
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ins.reg1direction shouldBe OperandDirection.READ
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ins.fpReg1direction shouldBe OperandDirection.UNUSED
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ins.reg1 shouldBe 42
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ins.reg2 shouldBe null
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@ -37,7 +37,7 @@ class TestInstructions: FunSpec({
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val ins = IRInstruction(Opcode.BZ, IRDataType.WORD, reg1=11, labelSymbol = "a.b.c")
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ins.opcode shouldBe Opcode.BZ
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ins.type shouldBe IRDataType.WORD
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ins.reg1direction shouldBe OperandDirection.INPUT
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ins.reg1direction shouldBe OperandDirection.READ
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ins.fpReg1direction shouldBe OperandDirection.UNUSED
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ins.reg1 shouldBe 11
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ins.reg2 shouldBe null
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@ -50,8 +50,8 @@ class TestInstructions: FunSpec({
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val ins = IRInstruction(Opcode.ADDR, IRDataType.WORD, reg1=11, reg2=22)
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ins.opcode shouldBe Opcode.ADDR
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ins.type shouldBe IRDataType.WORD
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ins.reg1direction shouldBe OperandDirection.INOUT
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ins.reg2direction shouldBe OperandDirection.INPUT
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ins.reg1direction shouldBe OperandDirection.READWRITE
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ins.reg2direction shouldBe OperandDirection.READ
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ins.fpReg1direction shouldBe OperandDirection.UNUSED
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ins.fpReg2direction shouldBe OperandDirection.UNUSED
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ins.reg1 shouldBe 11
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@ -63,8 +63,8 @@ class TestInstructions: FunSpec({
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val ins2 = IRInstruction(Opcode.SQRT, IRDataType.BYTE, reg1=11, reg2=22)
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ins2.opcode shouldBe Opcode.SQRT
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ins2.type shouldBe IRDataType.BYTE
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ins2.reg1direction shouldBe OperandDirection.OUTPUT
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ins2.reg2direction shouldBe OperandDirection.INPUT
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ins2.reg1direction shouldBe OperandDirection.WRITE
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ins2.reg2direction shouldBe OperandDirection.READ
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ins2.fpReg1direction shouldBe OperandDirection.UNUSED
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ins2.fpReg2direction shouldBe OperandDirection.UNUSED
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ins2.reg1 shouldBe 11
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@ -80,8 +80,8 @@ class TestInstructions: FunSpec({
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ins.type shouldBe IRDataType.FLOAT
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ins.reg1direction shouldBe OperandDirection.UNUSED
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ins.reg2direction shouldBe OperandDirection.UNUSED
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ins.fpReg1direction shouldBe OperandDirection.OUTPUT
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ins.fpReg2direction shouldBe OperandDirection.INPUT
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ins.fpReg1direction shouldBe OperandDirection.WRITE
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ins.fpReg2direction shouldBe OperandDirection.READ
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ins.fpReg1 shouldBe 1
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ins.fpReg2 shouldBe 2
|
||||
ins.reg1 shouldBe null
|
||||
@ -115,8 +115,8 @@ class TestInstructions: FunSpec({
|
||||
Opcode.values().forEach {
|
||||
val fmt = instructionFormats.getValue(it)
|
||||
fmt.values.forEach { format ->
|
||||
require(format.reg2==OperandDirection.UNUSED || format.reg2==OperandDirection.INPUT) {"reg2 can only be used as input"}
|
||||
require(format.fpReg2==OperandDirection.UNUSED || format.fpReg2==OperandDirection.INPUT) {"fpReg2 can only be used as input"}
|
||||
require(format.reg2==OperandDirection.UNUSED || format.reg2==OperandDirection.READ) {"reg2 can only be used as input"}
|
||||
require(format.fpReg2==OperandDirection.UNUSED || format.fpReg2==OperandDirection.READ) {"fpReg2 can only be used as input"}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user