IR: don't lose inline asm chunks, fix carry behavior for multi-shifts

This commit is contained in:
Irmen de Jong 2025-01-04 21:19:52 +01:00
parent 823eaa8918
commit 407773bda2
3 changed files with 12 additions and 16 deletions

View File

@ -199,6 +199,8 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
IRInlineAsmChunk(label, candidate.assembly, candidate.isIR, candidate.next)
else
candidate
} else {
chunks += candidate
}
}
is IRInlineBinaryChunk -> {
@ -210,6 +212,8 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
IRInlineBinaryChunk(label, candidate.data, candidate.next)
else
candidate
} else {
chunks += candidate
}
}
}

View File

@ -181,12 +181,12 @@ xor reg1, value - reg1 = reg1 bitwise xor value
xorm reg1, address - memory = memory bitwise xor reg1
inv reg1 - reg1 = bitwise invert of reg1 (all bits flipped)
invm address - memory = bitwise invert of that memory (all bits flipped)
asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + set Carry to shifted bit
asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + Carry is undefined
lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + Carry is undefined
lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + Carry is undefined
asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + Carry is undefined
lsrnm reg1, address - multi-shift memoryright by reg1 bits + Carry is undefined
lslnm reg1, address - multi-shift memory left by reg1 bits + Carry is undefined
asr reg1 - shift reg1 right by 1 bits (signed) + set Carry to shifted bit
lsr reg1 - shift reg1 right by 1 bits + set Carry to shifted bit
lsl reg1 - shift reg1 left by 1 bits + set Carry to shifted bit

View File

@ -1849,7 +1849,6 @@ class VirtualMachine(irProgram: IRProgram) {
private fun InsASRN(i: IRInstruction) {
val (left: Int, right: Int) = getLogicalOperandsS(i)
statusCarry = (left and 1)!=0
when(i.type!!) {
IRDataType.BYTE -> registers.setSB(i.reg1!!, (left shr right).toByte())
IRDataType.WORD -> registers.setSW(i.reg1!!, (left shr right).toShort())
@ -1864,12 +1863,10 @@ class VirtualMachine(irProgram: IRProgram) {
when(i.type!!) {
IRDataType.BYTE -> {
val memvalue = memory.getSB(address).toInt()
statusCarry = (memvalue and 1)!=0
memory.setSB(address, (memvalue shr operand).toByte())
}
IRDataType.WORD -> {
val memvalue = memory.getSW(address).toInt()
statusCarry = (memvalue and 1)!=0
memory.setSW(address, (memvalue shr operand).toShort())
}
IRDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
@ -1914,7 +1911,6 @@ class VirtualMachine(irProgram: IRProgram) {
private fun InsLSRN(i: IRInstruction) {
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
statusCarry = (left and 1u)!=0u
when(i.type!!) {
IRDataType.BYTE -> registers.setUB(i.reg1!!, (left shr right.toInt()).toUByte())
IRDataType.WORD -> registers.setUW(i.reg1!!, (left shr right.toInt()).toUShort())
@ -1929,12 +1925,10 @@ class VirtualMachine(irProgram: IRProgram) {
when(i.type!!) {
IRDataType.BYTE -> {
val memvalue = memory.getUB(address).toInt()
statusCarry = (memvalue and 1)!=0
memory.setUB(address, (memvalue shr operand).toUByte())
}
IRDataType.WORD -> {
val memvalue = memory.getUW(address).toInt()
statusCarry = (memvalue and 1)!=0
memory.setUW(address, (memvalue shr operand).toUShort())
}
IRDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
@ -1981,11 +1975,9 @@ class VirtualMachine(irProgram: IRProgram) {
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
when(i.type!!) {
IRDataType.BYTE -> {
statusCarry = (left and 0x80u)!=0u
registers.setUB(i.reg1!!, (left shl right.toInt()).toUByte())
}
IRDataType.WORD -> {
statusCarry = (left and 0x8000u)!=0u
registers.setUW(i.reg1!!, (left shl right.toInt()).toUShort())
}
IRDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
@ -1999,12 +1991,12 @@ class VirtualMachine(irProgram: IRProgram) {
when(i.type!!) {
IRDataType.BYTE -> {
val memvalue = memory.getUB(address).toInt()
statusCarry = (memvalue and 0x80)!=0
memory.setUB(address, (memvalue shl operand).toUByte())
}
IRDataType.WORD -> {
val memvalue = memory.getUW(address).toInt()
statusCarry = (memvalue and 0x8000)!=0
val x1 = (memvalue shl operand)
val x2 = x1.toUShort()
memory.setUW(address, (memvalue shl operand).toUShort())
}
IRDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")