IR: rename <CODE> to <CHUNK> , put the code lines in a new sub node <CODE> for improved xml structure

docs/source/todo.rst

@@ -1,7 +1,7 @@
 TODO
 ====
 
-IR: rename <CODE> to <CHUNK> , put the code lines in a new sub node <CODE> for improved xml structure.
+IR: register type error when compiling examples/textelite with expericodegen
 TestVMCodegen: add tests for SSA block split/joins/check last instruction to be a valid SSE block ender
 
 

intermediate/src/prog8/intermediate/IRFileReader.kt

@@ -404,7 +404,7 @@ class IRFileReader {
         require(start.name.localPart=="INITGLOBALS") { "missing INITGLOBALS" }
         skipText(reader)
         val chunk: IRCodeChunk = if(reader.peek().isStartElement)
-            parseCodeChunk(reader)
+            parseCodeBlock(reader)
         else
             IRCodeChunk(null, null)
         skipText(reader)
@@ -412,10 +412,10 @@ class IRFileReader {
         return chunk
     }
 
-    private fun parseCodeChunk(reader: XMLEventReader): IRCodeChunk {
+    private fun parseCodeBlock(reader: XMLEventReader): IRCodeChunk {
         skipText(reader)
-        val codeStart = reader.nextEvent().asStartElement()
-        require(codeStart.name.localPart=="CODE") { "missing CODE" }
+        val chunkStart = reader.nextEvent().asStartElement()
+        require(chunkStart.name.localPart=="CHUNK") { "missing CHUNK" }
 
         // now skip <REGS> as it is informational
         val regsStart = reader.nextEvent().asStartElement()
@@ -428,7 +428,10 @@ class IRFileReader {
             reader.nextEvent()  // skip the P8SRC node
             while(!reader.nextEvent().isEndElement) { /* skip until end of P8SRC node */ }
         }
-        val label = codeStart.attributes.asSequence().singleOrNull { it.name.localPart == "LABEL" }?.value?.ifBlank { null }
+        val label = chunkStart.attributes.asSequence().singleOrNull { it.name.localPart == "LABEL" }?.value?.ifBlank { null }
+
+        val codeStart = reader.nextEvent().asStartElement()
+        require(codeStart.name.localPart=="CODE") { "missing CODE" }
         val text = readText(reader).trim()
         val chunk = IRCodeChunk(label, null)
         if(text.isNotBlank()) {
@@ -447,7 +450,8 @@ class IRFileReader {
             }
         }
 
-        require(reader.nextEvent().isEndElement)
+        require(reader.nextEvent().isEndElement)    // close CODE
+        require(reader.nextEvent().isEndElement)    // close CHUNK
         return chunk
     }
 
@@ -484,8 +488,8 @@ class IRFileReader {
                 "ASMSUB" -> block += parseAsmSubroutine(reader)
                 "ASM" -> block += parseInlineAssembly(reader)
                 "BYTES" -> block += parseBinaryBytes(reader)
-                "CODE" -> {
-                    val chunk = parseCodeChunk(reader)
+                "CB" -> {
+                    val chunk = parseCodeBlock(reader)
                     if(chunk.isNotEmpty() || chunk.label==null)
                         throw IRParseException("code chunk in block should only contain a label name")
                     block += chunk
@@ -513,7 +517,7 @@ class IRFileReader {
         skipText(reader)
         while(reader.peek().isStartElement) {
             sub += when(reader.peek().asStartElement().name.localPart) {
-                "CODE" -> parseCodeChunk(reader)
+                "CHUNK" -> parseCodeBlock(reader)
                 "BYTES" -> parseBinaryBytes(reader)
                 "ASM" -> parseInlineAssembly(reader)
                 else -> throw IRParseException("invalid line in SUB: ${reader.peek()}")

intermediate/src/prog8/intermediate/IRFileWriter.kt

@@ -151,15 +151,15 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
                 regs.append(" write: ${usedRegs.writeFpRegs.toSortedMap().map { (reg, amount) -> "fr$reg=${amount}" }}\n")
         }
 
-        xml.writeStartElement("CODE")
+        xml.writeStartElement("CHUNK")
         chunk.label?.let { xml.writeAttribute("LABEL", chunk.label) }
 
         // xml.writeAttribute("used-registers", chunk.usedRegisters().toString())
         xml.writeStartElement("REGS")
         xml.writeCData(regs.toString())
         xml.writeEndElement()
-
         writeSourcelines(xml, chunk)
+        xml.writeStartElement("CODE")
         xml.writeCharacters("\n")
         chunk.instructions.forEach { instr ->
             numInstr++
@@ -167,6 +167,7 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
             xml.writeCharacters("\n")
         }
         xml.writeEndElement()
+        xml.writeEndElement()
         xml.writeCharacters("\n")
     }
 

intermediate/test/TestIRFileInOut.kt

@@ -80,18 +80,18 @@ ubyte main.thing=42
 </MEMORYSLABS>
 
 <INITGLOBALS>
-<CODE><REGS>dummy</REGS>
+<CHUNK><REGS>dummy</REGS><CODE>
 load.b r1,42
-</CODE>
+</CODE></CHUNK>
 </INITGLOBALS>
 
 <BLOCK NAME="main" ADDRESS="" LIBRARY="false" FORCEOUTPUT="false" NOPREFIXING="false" VERAFXMULS="false" ALIGN="NONE" POS="[examples/test.p8: line 2 col 2-5]">
 <SUB NAME="main.start" RETURNS="" POS="[examples/test.p8: line 4 col 6-8]">
 <PARAMS>
 </PARAMS>
-<CODE LABEL="main.start"><REGS>dummy</REGS>
+<CHUNK LABEL="main.start"><REGS>dummy</REGS><CODE>
 return
-</CODE>
+</CODE></CHUNK>
 </SUB>
 </BLOCK>
 
@@ -103,9 +103,9 @@ uword sys.wait.jiffies
 <ASM LABEL="sys.wait" IR="true" POS="[library:/prog8lib/virtual/syslib.p8: line 17 col 10-13]">
             loadm.w r0,sys.wait.jiffies
 </ASM>
-<CODE><REGS>dummy</REGS>
+<CHUNK><REGS>dummy</REGS><CODE>
 return
-</CODE>
+</CODE></CHUNK>
 </SUB>
 </BLOCK>
 </PROGRAM>