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cpu unit test suite ported from Py65
This commit is contained in:
Irmen de Jong
parent
bed0e33b4f
commit
42f8e98cab
@ -8,9 +8,9 @@ interface ICpu {
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fun disassemble(component: MemMappedComponent, from: Address, to: Address) =
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disassemble(component.cloneMem(), component.startAddress, from, to)
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fun dumpState()
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fun clock()
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fun reset()
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fun step()
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var tracing: Boolean
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val totalCycles: Int
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@ -98,17 +98,30 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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Z = (byte and 0b00000010) != 0
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C = (byte and 0b00000001) != 0
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}
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override fun toString(): String {
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return asByte().toString(2).padStart(8, '0')
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}
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override fun hashCode(): Int = asByte().toInt()
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override fun equals(other: Any?): Boolean {
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if(other !is StatusRegister)
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return false
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return asByte()==other.asByte()
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}
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}
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private var instrCycles: Int = 0
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private var A: Int = 0
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private var X: Int = 0
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private var Y: Int = 0
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private var sp: Int = 0
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private var pc: Address = 0
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private val status = StatusRegister()
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private var currentOpcode: Int = 0
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var instrCycles: Int = 0
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var A: Int = 0
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var X: Int = 0
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var Y: Int = 0
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var SP: Int = 0
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var PC: Address = 0
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val Status = StatusRegister()
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var currentOpcode: Int = 0
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var waiting: Boolean = false // 65c02
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private lateinit var currentInstruction: Instruction
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// data byte from the instruction (only set when addr.mode is Accumulator, Immediate or Implied)
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@ -221,30 +234,31 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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}
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override fun reset() {
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sp = 0xfd
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pc = readWord(RESET_vector)
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SP = 0xfd
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PC = readWord(RESET_vector)
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A = 0
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X = 0
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Y = 0
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status.C = false
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status.Z = false
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status.I = false
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status.D = false
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status.B = false
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status.V = false
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status.N = false
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Status.C = false
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Status.Z = false
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Status.I = false
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Status.D = false
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Status.B = false
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Status.V = false
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Status.N = false
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instrCycles = 8
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currentOpcode = 0
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currentInstruction = opcodes[0]
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waiting = false
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}
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override fun clock() {
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if (instrCycles == 0) {
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currentOpcode = read(pc++)
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currentOpcode = read(PC++)
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currentInstruction = opcodes[currentOpcode]
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if (tracing) {
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dumpState()
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printState()
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}
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if (!currentInstruction.official && !illegalInstrsAllowed) {
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@ -260,19 +274,25 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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totalCycles++
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}
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override fun dumpState() {
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println("cycle:$totalCycles - pc=${hexW(pc)} " +
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override fun step() {
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// step a whole instruction
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while(instrCycles>0) clock() // instruction subcycles
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clock() // the actual instruction execution cycle
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}
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fun printState() {
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println("cycle:$totalCycles - pc=${hexW(PC)} " +
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"A=${hexB(A)} " +
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"X=${hexB(X)} " +
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"Y=${hexB(Y)} " +
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"SP=${hexB(sp)} " +
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" n=" + (if (status.N) "1" else "0") +
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" v=" + (if (status.V) "1" else "0") +
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" b=" + (if (status.B) "1" else "0") +
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" d=" + (if (status.D) "1" else "0") +
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" i=" + (if (status.I) "1" else "0") +
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" z=" + (if (status.Z) "1" else "0") +
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" c=" + (if (status.C) "1" else "0") +
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"SP=${hexB(SP)} " +
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" n=" + (if (Status.N) "1" else "0") +
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" v=" + (if (Status.V) "1" else "0") +
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" b=" + (if (Status.B) "1" else "0") +
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" d=" + (if (Status.D) "1" else "0") +
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" i=" + (if (Status.I) "1" else "0") +
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" z=" + (if (Status.Z) "1" else "0") +
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" c=" + (if (Status.C) "1" else "0") +
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" icycles=$instrCycles instr=${hexB(currentOpcode)}:${currentInstruction.mnemonic}"
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)
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}
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@ -306,9 +326,9 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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private fun amRel() {
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val relative = readPc().toByte()
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fetchedAddress = if (relative >= 0x80)
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pc - (256 - relative)
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PC - (256 - relative)
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else
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pc + relative
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PC + relative
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}
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private fun amAbs() {
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@ -362,7 +382,7 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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fetchedAddress = Y + (lo or (hi shl 8))
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}
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private fun readPc(): Int = bus.read(pc++).toInt()
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private fun readPc(): Int = bus.read(PC++).toInt()
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private fun pushStackAddr(address: Address) {
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val lo = address and 255
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@ -376,13 +396,13 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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}
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private fun pushStack(data: Int) {
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write(sp or 0x0100, data)
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sp = (sp - 1) and 0xff
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write(SP or 0x0100, data)
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SP = (SP - 1) and 0xff
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}
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private fun popStack(): Int {
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sp = (sp + 1) and 0xff
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return read(sp or 0x0100)
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SP = (SP + 1) and 0xff
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return read(SP or 0x0100)
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}
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private fun popStackAddr(): Address {
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@ -668,113 +688,113 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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} else {
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read(fetchedAddress)
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}
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if (status.D) {
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if (Status.D) {
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// BCD add
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var lo = (A and 0x0f) + (operand and 0x0f) + if (status.C) 1 else 0
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var lo = (A and 0x0f) + (operand and 0x0f) + if (Status.C) 1 else 0
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if (lo and 0xff > 9) lo += 6
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var hi = (A shr 4) + (operand shr 4) + if (lo > 15) 1 else 0
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if (hi and 0xff > 9) hi += 6
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var result = lo and 0x0f or (hi shl 4)
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result = result and 0xff
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status.C = hi > 15
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status.Z = result == 0
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status.V = false // BCD never sets overflow flag
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status.N = false // BCD is never negative on NMOS 6502 (bug)
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Status.C = hi > 15
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Status.Z = result == 0
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Status.V = false // BCD never sets overflow flag
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Status.N = false // BCD is never negative on NMOS 6502 (bug)
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} else {
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// normal add
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val result = A + operand + if (status.C) 1 else 0
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status.C = result > 255
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status.V = (A xor operand).inv() and (A xor result) and 0x0080 != 0
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val result = A + operand + if (Status.C) 1 else 0
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Status.C = result > 255
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Status.V = (A xor operand).inv() and (A xor result) and 0x0080 != 0
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A = result and 255
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status.N = (A and 0b10000000) != 0
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status.Z = A == 0
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Status.N = (A and 0b10000000) != 0
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Status.Z = A == 0
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}
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}
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private fun iAnd() {
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A = A and fetchedData
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status.Z = A == 0
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status.N = (A and 0b10000000) != 0
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Status.Z = A == 0
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Status.N = (A and 0b10000000) != 0
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}
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private fun iAsl() {
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if (currentInstruction.mode == AddrMode.Acc) {
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status.C = (A and 0b10000000) == 1
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Status.C = (A and 0b10000000) == 1
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A = (A shl 1) and 255
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status.Z = A == 0
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status.N = (A and 0b10000000) == 1
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Status.Z = A == 0
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Status.N = (A and 0b10000000) == 1
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} else {
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val data = read(fetchedAddress)
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status.C = (data and 0b10000000) == 1
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Status.C = (data and 0b10000000) == 1
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val shifted = (data shl 1) and 255
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write(fetchedAddress, shifted)
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status.Z = shifted == 0
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status.N = (shifted and 0b10000000) == 1
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Status.Z = shifted == 0
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Status.N = (shifted and 0b10000000) == 1
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}
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}
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private fun iBcc() {
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if (!status.C) pc = fetchedAddress
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if (!Status.C) PC = fetchedAddress
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}
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private fun iBcs() {
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if (status.C) pc = fetchedAddress
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if (Status.C) PC = fetchedAddress
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}
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private fun iBeq() {
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if (status.Z) pc = fetchedAddress
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if (Status.Z) PC = fetchedAddress
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}
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private fun iBit() {
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status.Z = (A and fetchedData) == 0
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status.V = (fetchedData and 0b01000000) != 0
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status.N = (fetchedData and 0b10000000) != 0
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Status.Z = (A and fetchedData) == 0
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Status.V = (fetchedData and 0b01000000) != 0
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Status.N = (fetchedData and 0b10000000) != 0
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}
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private fun iBmi() {
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if (status.N) pc = fetchedAddress
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if (Status.N) PC = fetchedAddress
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}
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private fun iBne() {
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if (!status.Z) pc = fetchedAddress
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if (!Status.Z) PC = fetchedAddress
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}
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private fun iBpl() {
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if (!status.N) pc = fetchedAddress
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if (!Status.N) PC = fetchedAddress
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}
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private fun iBrk() {
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pc++
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status.I = true
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status.B = true
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pushStackAddr(pc)
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pushStack(status)
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status.B = false
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pc = readWord(IRQ_vector)
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PC++
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Status.I = true
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Status.B = true
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pushStackAddr(PC)
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pushStack(Status)
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Status.B = false
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PC = readWord(IRQ_vector)
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}
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private fun iBvc() {
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if (!status.V) pc = fetchedAddress
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if (!Status.V) PC = fetchedAddress
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}
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private fun iBvs() {
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if (status.V) pc = fetchedAddress
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if (Status.V) PC = fetchedAddress
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}
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private fun iClc() {
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status.C = false
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Status.C = false
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}
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private fun iCld() {
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status.D = false
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Status.D = false
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}
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private fun iCli() {
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status.I = false
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Status.I = false
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}
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private fun iClv() {
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status.V = false
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Status.V = false
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}
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private fun iCmp() {
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@ -784,9 +804,9 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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} else {
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read(fetchedAddress)
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}
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status.C = A >= fetched
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status.Z = A == fetched
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status.N = ((A - fetched) and 0b10000000) == 1
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Status.C = A >= fetched
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Status.Z = A == fetched
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Status.N = ((A - fetched) and 0b10000000) == 1
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}
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private fun iCpx() {
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@ -796,9 +816,9 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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} else {
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read(fetchedAddress)
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}
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status.C = X >= fetched
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status.Z = X == fetched
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status.N = ((X - fetched) and 0b10000000) == 1
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Status.C = X >= fetched
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Status.Z = X == fetched
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Status.N = ((X - fetched) and 0b10000000) == 1
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}
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private fun iCpy() {
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@ -808,28 +828,28 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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} else {
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read(fetchedAddress)
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}
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status.C = Y >= fetched
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status.Z = Y == fetched
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status.N = ((Y - fetched) and 0b10000000) == 1
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Status.C = Y >= fetched
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Status.Z = Y == fetched
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Status.N = ((Y - fetched) and 0b10000000) == 1
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}
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private fun iDec() {
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val data = (read(fetchedAddress) - 1) and 255
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write(fetchedAddress, data)
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status.Z = data == 0
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status.N = (data and 0b10000000) == 1
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Status.Z = data == 0
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Status.N = (data and 0b10000000) == 1
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}
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private fun iDex() {
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X = (X - 1) and 255
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status.Z = X == 0
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status.N = (X and 0b10000000) == 1
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Status.Z = X == 0
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Status.N = (X and 0b10000000) == 1
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}
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private fun iDey() {
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Y = (Y - 1) and 255
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status.Z = Y == 0
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status.N = (Y and 0b10000000) == 1
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Status.Z = Y == 0
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Status.N = (Y and 0b10000000) == 1
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}
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private fun iEor() {
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@ -838,36 +858,36 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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} else {
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A xor read(fetchedAddress)
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}
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status.Z = A == 0
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status.N = (A and 0b10000000) == 1
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Status.Z = A == 0
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Status.N = (A and 0b10000000) == 1
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}
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private fun iInc() {
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val data = (read(fetchedAddress) + 1) and 255
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write(fetchedAddress, data)
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status.Z = data == 0
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status.N = (data and 0b10000000) == 1
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Status.Z = data == 0
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Status.N = (data and 0b10000000) == 1
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}
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private fun iInx() {
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X = (X + 1) and 255
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status.Z = X == 0
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status.N = (X and 0b10000000) == 1
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Status.Z = X == 0
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Status.N = (X and 0b10000000) == 1
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}
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private fun iIny() {
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Y = (Y + 1) and 255
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status.Z = Y == 0
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status.N = (Y and 0b10000000) == 1
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Status.Z = Y == 0
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Status.N = (Y and 0b10000000) == 1
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}
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private fun iJmp() {
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pc = fetchedAddress
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PC = fetchedAddress
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}
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private fun iJsr() {
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pushStackAddr(pc)
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pc = fetchedAddress
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pushStackAddr(PC)
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PC = fetchedAddress
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}
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private fun iLda() {
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@ -875,8 +895,8 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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fetchedData
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else
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read(fetchedAddress)
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status.Z = A == 0
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status.N = (A and 0b10000000) == 1
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Status.Z = A == 0
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Status.N = (A and 0b10000000) == 1
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}
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private fun iLdx() {
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@ -884,8 +904,8 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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fetchedData
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else
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read(fetchedAddress)
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status.Z = X == 0
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status.N = (X and 0b10000000) == 1
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Status.Z = X == 0
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Status.N = (X and 0b10000000) == 1
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}
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private fun iLdy() {
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@ -893,23 +913,23 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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fetchedData
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else
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read(fetchedAddress)
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status.Z = Y == 0
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status.N = (Y and 0b10000000) == 1
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Status.Z = Y == 0
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Status.N = (Y and 0b10000000) == 1
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}
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private fun iLsr() {
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if (currentInstruction.mode == AddrMode.Acc) {
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status.C = (A and 1) == 1
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Status.C = (A and 1) == 1
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A = A ushr 1
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status.Z = A == 0
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status.N = (A and 0b10000000) == 1
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Status.Z = A == 0
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Status.N = (A and 0b10000000) == 1
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} else {
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val data = read(fetchedAddress)
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status.C = (data and 1) == 1
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Status.C = (data and 1) == 1
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val shifted = data ushr 1
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||||
write(fetchedAddress, shifted)
|
||||
status.Z = shifted == 0
|
||||
status.N = (shifted and 0b10000000) == 1
|
||||
Status.Z = shifted == 0
|
||||
Status.N = (shifted and 0b10000000) == 1
|
||||
}
|
||||
}
|
||||
|
||||
@ -920,8 +940,8 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
|
||||
A or fetchedData
|
||||
else
|
||||
A or read(fetchedAddress)
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) == 1
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) == 1
|
||||
}
|
||||
|
||||
private fun iPha() {
|
||||
@ -929,60 +949,60 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
|
||||
}
|
||||
|
||||
private fun iPhp() {
|
||||
pushStack(status)
|
||||
pushStack(Status)
|
||||
}
|
||||
|
||||
private fun iPla() {
|
||||
A = popStack()
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) == 1
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) == 1
|
||||
}
|
||||
|
||||
private fun iPlp() {
|
||||
status.fromByte(popStack())
|
||||
Status.fromByte(popStack())
|
||||
}
|
||||
|
||||
private fun iRol() {
|
||||
val oldCarry = status.C
|
||||
val oldCarry = Status.C
|
||||
if (currentInstruction.mode == AddrMode.Acc) {
|
||||
status.C = (A and 0b10000000) == 1
|
||||
Status.C = (A and 0b10000000) == 1
|
||||
A = (A shl 1) or (if (oldCarry) 1 else 0)
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) == 1
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) == 1
|
||||
} else {
|
||||
val data = read(fetchedAddress)
|
||||
status.C = (data and 0b10000000) == 1
|
||||
Status.C = (data and 0b10000000) == 1
|
||||
val shifted = (data shl 1) or (if (oldCarry) 1 else 0) and 255
|
||||
write(fetchedAddress, shifted)
|
||||
status.Z = shifted == 0
|
||||
status.N = (shifted and 0b10000000) == 1
|
||||
Status.Z = shifted == 0
|
||||
Status.N = (shifted and 0b10000000) == 1
|
||||
}
|
||||
}
|
||||
|
||||
private fun iRor() {
|
||||
val oldCarry = status.C
|
||||
val oldCarry = Status.C
|
||||
if (currentInstruction.mode == AddrMode.Acc) {
|
||||
status.C = (A and 1) == 1
|
||||
Status.C = (A and 1) == 1
|
||||
A = (A ushr 1) or (if (oldCarry) 0b10000000 else 0)
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) == 1
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) == 1
|
||||
} else {
|
||||
val data = read(fetchedAddress)
|
||||
status.C = (data and 1) == 1
|
||||
Status.C = (data and 1) == 1
|
||||
val shifted = (data ushr 1) or (if (oldCarry) 0b10000000 else 0)
|
||||
write(fetchedAddress, shifted)
|
||||
status.Z = shifted == 0
|
||||
status.N = (shifted and 0b10000000) == 1
|
||||
Status.Z = shifted == 0
|
||||
Status.N = (shifted and 0b10000000) == 1
|
||||
}
|
||||
}
|
||||
|
||||
private fun iRti() {
|
||||
status.fromByte(popStack())
|
||||
pc = popStackAddr()
|
||||
Status.fromByte(popStack())
|
||||
PC = popStackAddr()
|
||||
}
|
||||
|
||||
private fun iRts() {
|
||||
pc = popStackAddr()
|
||||
PC = popStackAddr()
|
||||
}
|
||||
|
||||
private fun iSbc() {
|
||||
@ -991,39 +1011,39 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
|
||||
} else {
|
||||
read(fetchedAddress)
|
||||
}
|
||||
if (status.D) {
|
||||
var lo = (A and 0x0f) - (operand and 0x0f) - if (status.C) 0 else 1
|
||||
if (Status.D) {
|
||||
var lo = (A and 0x0f) - (operand and 0x0f) - if (Status.C) 0 else 1
|
||||
if (lo and 0x10 != 0) lo -= 6
|
||||
var h = (A shr 4) - (operand shr 4) - if (lo and 0x10 != 0) 1 else 0
|
||||
if (h and 0x10 != 0) h -= 6
|
||||
val result = lo and 0x0f or (h shl 4 and 0xff)
|
||||
status.C = h and 255 < 15
|
||||
status.Z = result == 0
|
||||
status.V = false // BCD never sets overflow flag
|
||||
status.N = false // BCD is never negative on NMOS 6502 (bug)
|
||||
Status.C = h and 255 < 15
|
||||
Status.Z = result == 0
|
||||
Status.V = false // BCD never sets overflow flag
|
||||
Status.N = false // BCD is never negative on NMOS 6502 (bug)
|
||||
A = result and 255
|
||||
} else {
|
||||
// normal sub
|
||||
val invertedOperand = operand xor 255
|
||||
val result = A + invertedOperand + if (status.C) 1 else 0
|
||||
status.C = result > 255
|
||||
status.V = (A xor invertedOperand) and (A xor result) and 0x0080 != 0
|
||||
val result = A + invertedOperand + if (Status.C) 1 else 0
|
||||
Status.C = result > 255
|
||||
Status.V = (A xor invertedOperand) and (A xor result) and 0x0080 != 0
|
||||
A = result and 255
|
||||
status.N = (A and 0b10000000) != 0
|
||||
status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) != 0
|
||||
Status.Z = A == 0
|
||||
}
|
||||
}
|
||||
|
||||
private fun iSec() {
|
||||
status.C = true
|
||||
Status.C = true
|
||||
}
|
||||
|
||||
private fun iSed() {
|
||||
status.D = true
|
||||
Status.D = true
|
||||
}
|
||||
|
||||
private fun iSei() {
|
||||
status.I = true
|
||||
Status.I = true
|
||||
}
|
||||
|
||||
private fun iSta() {
|
||||
@ -1040,36 +1060,36 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
|
||||
|
||||
private fun iTax() {
|
||||
X = A
|
||||
status.Z = X == 0
|
||||
status.N = (X and 0b10000000) != 0
|
||||
Status.Z = X == 0
|
||||
Status.N = (X and 0b10000000) != 0
|
||||
}
|
||||
|
||||
private fun iTay() {
|
||||
Y = A
|
||||
status.Z = Y == 0
|
||||
status.N = (Y and 0b10000000) != 0
|
||||
Status.Z = Y == 0
|
||||
Status.N = (Y and 0b10000000) != 0
|
||||
}
|
||||
|
||||
private fun iTsx() {
|
||||
X = status.asByte().toInt()
|
||||
status.Z = X == 0
|
||||
status.N = (X and 0b10000000) != 0
|
||||
X = Status.asByte().toInt()
|
||||
Status.Z = X == 0
|
||||
Status.N = (X and 0b10000000) != 0
|
||||
}
|
||||
|
||||
private fun iTxa() {
|
||||
A = X
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) != 0
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) != 0
|
||||
}
|
||||
|
||||
private fun iTxs() {
|
||||
status.fromByte(X)
|
||||
Status.fromByte(X)
|
||||
}
|
||||
|
||||
private fun iTya() {
|
||||
A = Y
|
||||
status.Z = A == 0
|
||||
status.N = (A and 0b10000000) != 0
|
||||
Status.Z = A == 0
|
||||
Status.N = (A and 0b10000000) != 0
|
||||
}
|
||||
|
||||
// unofficial/illegal instructions
|
||||
|
||||
@ -11,6 +11,9 @@ class Ram(startAddress: Address, endAddress: Address): MemMappedComponent(startA
|
||||
memory[address-startAddress] = data
|
||||
}
|
||||
|
||||
operator fun get(address: Address) = read(address)
|
||||
operator fun set(address: Address, data: UByte) = write(address, data)
|
||||
|
||||
override fun cloneMem(): Array<UByte> = memory.toTypedArray()
|
||||
|
||||
override fun clock() { }
|
||||
|
||||
321
sim65/test/Test6502.kt
Normal file
321
sim65/test/Test6502.kt
Normal file
@ -0,0 +1,321 @@
|
||||
import org.junit.jupiter.api.Test
|
||||
import org.junit.jupiter.api.TestInstance
|
||||
import kotlin.test.*
|
||||
|
||||
|
||||
/*
|
||||
|
||||
Unit test suite adapted from Py65 https://github.com/mnaberez/py65
|
||||
|
||||
Copyright (c) 2008-2018, Mike Naberezny and contributors.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
@TestInstance(TestInstance.Lifecycle.PER_METHOD)
|
||||
class Test6502 : TestCommon6502() {
|
||||
// NMOS 6502 tests
|
||||
|
||||
// ADC Indirect, Indexed (X)
|
||||
|
||||
@Test
|
||||
fun test_adc_ind_indexed_has_page_wrap_bug() {
|
||||
mpu.A = 0x01
|
||||
mpu.X = 0xFF
|
||||
// $0000 ADC ($80,X)
|
||||
// $007f Vector to $BBBB (read if page wrapped)
|
||||
// $017f Vector to $ABCD (read if no page wrap)
|
||||
writeMem(memory, 0x0000, listOf(0x61, 0x80))
|
||||
writeMem(memory, 0x007f, listOf(0xBB, 0xBB))
|
||||
writeMem(memory, 0x017f, listOf(0xCD, 0xAB))
|
||||
memory[0xABCD] = 0x01
|
||||
memory[0xBBBB] = 0x02
|
||||
mpu.step()
|
||||
assertEquals(0x03, mpu.A)
|
||||
}
|
||||
|
||||
// ADC Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_adc_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0x42
|
||||
mpu.Y = 0x02
|
||||
// $1000 ADC ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0x71, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x14 // read if no page wrap
|
||||
memory[0x0012] = 0x42 // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x84, mpu.A)
|
||||
}
|
||||
|
||||
// LDA Zero Page, X-Indexed
|
||||
|
||||
@Test
|
||||
fun test_lda_zp_x_indexed_page_wraps() {
|
||||
mpu.A = 0x00
|
||||
mpu.X = 0xFF
|
||||
// $0000 LDA $80,X
|
||||
writeMem(memory, 0x0000, listOf(0xB5, 0x80))
|
||||
memory[0x007F] = 0x42
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.PC)
|
||||
assertEquals(0x42, mpu.A)
|
||||
}
|
||||
|
||||
// AND Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_and_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0x42
|
||||
mpu.Y = 0x02
|
||||
// $1000 AND ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0x31, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x00 // read if no page wrap
|
||||
memory[0x0012] = 0xFF // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x42, mpu.A)
|
||||
}
|
||||
|
||||
// BRK
|
||||
|
||||
@Test
|
||||
fun test_brk_preserves_decimal_flag_when_it_is_set() {
|
||||
mpu.Status.D = true
|
||||
// $C000 BRK
|
||||
memory[0xC000] = 0x00
|
||||
mpu.PC = 0xC000
|
||||
mpu.step()
|
||||
assertTrue(mpu.Status.B)
|
||||
assertTrue(mpu.Status.D)
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_brk_preserves_decimal_flag_when_it_is_clear() {
|
||||
// $C000 BRK
|
||||
memory[0xC000] = 0x00
|
||||
mpu.PC = 0xC000
|
||||
mpu.step()
|
||||
assertTrue(mpu.Status.B)
|
||||
assertFalse(mpu.Status.D)
|
||||
}
|
||||
|
||||
// CMP Indirect, Indexed (X)
|
||||
|
||||
@Test
|
||||
fun test_cmp_ind_x_has_page_wrap_bug() {
|
||||
mpu.A = 0x42
|
||||
mpu.X = 0xFF
|
||||
// $0000 CMP ($80,X)
|
||||
// $007f Vector to $BBBB (read if page wrapped)
|
||||
// $017f Vector to $ABCD (read if no page wrap)
|
||||
writeMem(memory, 0x0000, listOf(0xC1, 0x80))
|
||||
writeMem(memory, 0x007f, listOf(0xBB, 0xBB))
|
||||
writeMem(memory, 0x017f, listOf(0xCD, 0xAB))
|
||||
memory[0xABCD] = 0x00
|
||||
memory[0xBBBB] = 0x42
|
||||
mpu.step()
|
||||
assertTrue(mpu.Status.Z)
|
||||
}
|
||||
|
||||
// CMP Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_cmp_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0x42
|
||||
mpu.Y = 0x02
|
||||
// $1000 CMP ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0xd1, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x14 // read if no page wrap
|
||||
memory[0x0012] = 0x42 // read if page wrapped
|
||||
mpu.step()
|
||||
assertTrue(mpu.Status.Z)
|
||||
}
|
||||
|
||||
// EOR Indirect, Indexed (X)
|
||||
|
||||
@Test
|
||||
fun test_eor_ind_x_has_page_wrap_bug() {
|
||||
mpu.A = 0xAA
|
||||
mpu.X = 0xFF
|
||||
// $0000 EOR ($80,X)
|
||||
// $007f Vector to $BBBB (read if page wrapped)
|
||||
// $017f Vector to $ABCD (read if no page wrap)
|
||||
writeMem(memory, 0x0000, listOf(0x41, 0x80))
|
||||
writeMem(memory, 0x007f, listOf(0xBB, 0xBB))
|
||||
writeMem(memory, 0x017f, listOf(0xCD, 0xAB))
|
||||
memory[0xABCD] = 0x00
|
||||
memory[0xBBBB] = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x55, mpu.A)
|
||||
}
|
||||
|
||||
// EOR Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_eor_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0xAA
|
||||
mpu.Y = 0x02
|
||||
// $1000 EOR ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0x51, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x00 // read if no page wrap
|
||||
memory[0x0012] = 0xFF // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x55, mpu.A)
|
||||
}
|
||||
|
||||
// LDA Indirect, Indexed (X)
|
||||
|
||||
@Test
|
||||
fun test_lda_ind_indexed_x_has_page_wrap_bug() {
|
||||
mpu.A = 0x00
|
||||
mpu.X = 0xff
|
||||
// $0000 LDA ($80,X)
|
||||
// $007f Vector to $BBBB (read if page wrapped)
|
||||
// $017f Vector to $ABCD (read if no page wrap)
|
||||
writeMem(memory, 0x0000, listOf(0xA1, 0x80))
|
||||
writeMem(memory, 0x007f, listOf(0xBB, 0xBB))
|
||||
writeMem(memory, 0x017f, listOf(0xCD, 0xAB))
|
||||
memory[0xABCD] = 0x42
|
||||
memory[0xBBBB] = 0xEF
|
||||
mpu.step()
|
||||
assertEquals(0xEF, mpu.A)
|
||||
}
|
||||
|
||||
// LDA Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_lda_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0x00
|
||||
mpu.Y = 0x02
|
||||
// $1000 LDA ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0xb1, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x14 // read if no page wrap
|
||||
memory[0x0012] = 0x42 // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x42, mpu.A)
|
||||
}
|
||||
|
||||
// LDA Zero Page, X-Indexed
|
||||
|
||||
@Test
|
||||
fun test_lda_zp_x_has_page_wrap_bug() {
|
||||
mpu.A = 0x00
|
||||
mpu.X = 0xFF
|
||||
// $0000 LDA $80,X
|
||||
writeMem(memory, 0x0000, listOf(0xB5, 0x80))
|
||||
memory[0x007F] = 0x42
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.PC)
|
||||
assertEquals(0x42, mpu.A)
|
||||
}
|
||||
|
||||
// JMP Indirect
|
||||
|
||||
@Test
|
||||
fun test_jmp_jumps_to_address_with_page_wrap_bug() {
|
||||
memory[0x00ff] = 0
|
||||
// $0000 JMP ($00)
|
||||
writeMem(memory, 0, listOf(0x6c, 0xff, 0x00))
|
||||
mpu.step()
|
||||
assertEquals(0x6c00, mpu.PC)
|
||||
assertEquals(5, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// ORA Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_ora_indexed_ind_y_has_page_wrap_bug() {
|
||||
mpu.PC = 0x1000
|
||||
mpu.A = 0x00
|
||||
mpu.Y = 0x02
|
||||
// $1000 ORA ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0x11, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x00 // read if no page wrap
|
||||
memory[0x0012] = 0x42 // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x42, mpu.A)
|
||||
}
|
||||
|
||||
// SBC Indexed, Indirect (Y)
|
||||
|
||||
@Test
|
||||
fun test_sbc_indexed_ind_y_has_page_wrap_bug() {
|
||||
|
||||
mpu.PC = 0x1000
|
||||
mpu.Status.C = true
|
||||
mpu.A = 0x42
|
||||
mpu.Y = 0x02
|
||||
// $1000 SBC ($FF),Y
|
||||
writeMem(memory, 0x1000, listOf(0xf1, 0xff))
|
||||
// Vector
|
||||
memory[0x00ff] = 0x10 // low byte
|
||||
memory[0x0100] = 0x20 // high byte if no page wrap
|
||||
memory[0x0000] = 0x00 // high byte if page wrapped
|
||||
// Data
|
||||
memory[0x2012] = 0x02 // read if no page wrap
|
||||
memory[0x0012] = 0x03 // read if page wrapped
|
||||
mpu.step()
|
||||
assertEquals(0x3f, mpu.A)
|
||||
}
|
||||
}
|
||||
25
sim65/test/Test6502CpuBasics.kt
Normal file
25
sim65/test/Test6502CpuBasics.kt
Normal file
@ -0,0 +1,25 @@
|
||||
import org.junit.jupiter.api.Test
|
||||
import sim65.components.Bus
|
||||
import sim65.components.Cpu6502
|
||||
import kotlin.test.assertEquals
|
||||
|
||||
class Test6502CpuBasics {
|
||||
|
||||
@Test
|
||||
fun testCpuFlagsAfterReset() {
|
||||
val cpu = Cpu6502(true)
|
||||
val bus = Bus()
|
||||
bus.add(cpu)
|
||||
cpu.reset()
|
||||
assertEquals(0xfd, cpu.SP)
|
||||
assertEquals(0xffff, cpu.PC)
|
||||
assertEquals(0, cpu.totalCycles)
|
||||
assertEquals(8, cpu.instrCycles)
|
||||
assertEquals(0, cpu.A)
|
||||
assertEquals(0, cpu.X)
|
||||
assertEquals(0, cpu.Y)
|
||||
assertEquals(0, cpu.currentOpcode)
|
||||
assertEquals(Cpu6502.StatusRegister(C = false, Z = false, I = false, D = false, B = false, V = false, N = false), cpu.Status)
|
||||
}
|
||||
|
||||
}
|
||||
1547
sim65/test/Test65C02.kt
Normal file
1547
sim65/test/Test65C02.kt
Normal file
File diff suppressed because it is too large
Load Diff
6866
sim65/test/TestCommon6502.kt
Normal file
6866
sim65/test/TestCommon6502.kt
Normal file
File diff suppressed because it is too large
Load Diff
@ -10,15 +10,15 @@ class TestDisassembler {
|
||||
fun testDisassembleAllOpcodes() {
|
||||
val cpu = Cpu6502(true)
|
||||
val memory = Ram(0, 0xffff)
|
||||
memory.load("test/testfiles/disassem_instr_test.prg", 0x1000-2)
|
||||
memory.load("test/testfiles/disassem_instr_test.prg", 0x1000 - 2)
|
||||
val result = cpu.disassemble(memory, 0x1000, 0x1221)
|
||||
assertEquals(256, result.size)
|
||||
assertEquals("\$1000 69 01 adc #\$01", result[0])
|
||||
|
||||
val reference = File("test/testfiles/disassem_ref_output.txt").readLines()
|
||||
assertEquals(256, reference.size)
|
||||
for(line in result.zip(reference)) {
|
||||
if(line.first!=line.second) {
|
||||
for (line in result.zip(reference)) {
|
||||
if (line.first != line.second) {
|
||||
fail("disassembled instruction mismatch: '${line.first}', expected '${line.second}'")
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user