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IR: optimize rol ror
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parent
03831a7394
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@ -41,10 +41,10 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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"reverse" -> funcReverse(call)
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"setlsb" -> funcSetLsbMsb(call, false)
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"setmsb" -> funcSetLsbMsb(call, true)
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"rol" -> funcRolRor(Opcode.ROXL, call)
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"ror" -> funcRolRor(Opcode.ROXR, call)
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"rol2" -> funcRolRor(Opcode.ROL, call)
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"ror2" -> funcRolRor(Opcode.ROR, call)
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"rol" -> funcRolRor(call)
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"ror" -> funcRolRor(call)
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"rol2" -> funcRolRor(call)
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"ror2" -> funcRolRor(call)
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"prog8_lib_stringcompare" -> funcStringCompare(call)
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"prog8_lib_square_byte" -> funcSquare(call, IRDataType.BYTE)
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"prog8_lib_square_word" -> funcSquare(call, IRDataType.WORD)
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@ -628,21 +628,51 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
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}
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private fun funcRolRor(opcode: Opcode, call: PtBuiltinFunctionCall): ExpressionCodeResult {
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// TODO optimize this to use the other ROL/ROR instructions too to always load into a temp reg
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val vmDt = irType(call.args[0].type)
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private fun funcRolRor(call: PtBuiltinFunctionCall): ExpressionCodeResult {
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val result = mutableListOf<IRCodeChunkBase>()
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val saveCarry = opcode in OpcodesThatDependOnCarry && !call.args[0].isSimple()
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val arg = call.args[0]
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val vmDt = irType(arg.type)
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val opcodeMemAndReg = when(call.name) {
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"rol" -> Opcode.ROXLM to Opcode.ROXL
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"ror" -> Opcode.ROXRM to Opcode.ROXR
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"rol2" -> Opcode.ROLM to Opcode.ROL
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"ror2" -> Opcode.RORM to Opcode.ROR
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else -> throw AssemblyError("wrong func")
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}
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val ident = arg as? PtIdentifier
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if(ident!=null) {
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addInstr(result, IRInstruction(opcodeMemAndReg.first, vmDt, labelSymbol = ident.name), null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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}
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val memAddr = (arg as? PtMemoryByte)?.address?.asConstInteger()
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if(memAddr!=null) {
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addInstr(result, IRInstruction(opcodeMemAndReg.first, vmDt, address = memAddr), null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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}
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val arr = (arg as? PtArrayIndexer)
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val index = arr?.index?.asConstInteger()
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if(arr!=null && index!=null) {
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val variable = arr.variable.name
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val itemsize = codeGen.program.memsizer.memorySize(arr.type)
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addInstr(result, IRInstruction(opcodeMemAndReg.first, vmDt, labelSymbol = variable, symbolOffset = index*itemsize), null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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}
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val opcode = opcodeMemAndReg.second
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val saveCarry = opcode in OpcodesThatDependOnCarry && !arg.isSimple()
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if(saveCarry)
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addInstr(result, IRInstruction(Opcode.PUSHST), null) // save Carry
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val tr = exprGen.translateExpression(call.args[0])
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val tr = exprGen.translateExpression(arg)
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addToResult(result, tr, tr.resultReg, -1)
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if(saveCarry)
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addInstr(result, IRInstruction(Opcode.POPST), null)
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addInstr(result, IRInstruction(opcode, vmDt, reg1 = tr.resultReg), null)
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if(saveCarry)
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addInstr(result, IRInstruction(Opcode.PUSHST), null) // save Carry
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result += assignRegisterTo(call.args[0], tr.resultReg)
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result += assignRegisterTo(arg, tr.resultReg)
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if(saveCarry)
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addInstr(result, IRInstruction(Opcode.POPST), null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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@ -1,9 +1,7 @@
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TODO
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====
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Mark had a compiler crash FatalAstException: invalid dt.
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IR: optimize funcRolRor()
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imageviewer: bmp palette is off (autumn.bmp)
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...
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