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optimize code for logical expressions more if right operand is simple
This commit is contained in:
Irmen de Jong
parent
18790d867c
commit
44ee4b989f
@ -360,43 +360,44 @@ internal class AssignmentAsmGen(private val program: Program,
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if(expr.operator in setOf("&", "|", "^", "and", "or", "xor")) {
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if(expr.left.inferType(program).isBytes && expr.right.inferType(program).isBytes &&
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expr.left.isSimple && expr.right.isSimple) {
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// if(expr.right is NumericLiteral || expr.right is IdentifierReference) {
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// TODO("optimized code for logical with right number/variable arg (byte)")
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// } else if(expr.left is NumericLiteral || expr.left is IdentifierReference) {
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// TODO("optimized code for logical with left number/variable arg (byte)")
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// }
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assignExpressionToRegister(expr.left, RegisterOrPair.A, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_B1", DataType.UBYTE, expr.definingSubroutine)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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when(expr.operator) {
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"&", "and" -> asmgen.out(" and P8ZP_SCRATCH_B1")
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"|", "or" -> asmgen.out(" ora P8ZP_SCRATCH_B1")
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"^", "xor" -> asmgen.out(" eor P8ZP_SCRATCH_B1")
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else -> throw AssemblyError("invalid operator")
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if(expr.right is NumericLiteral || expr.right is IdentifierReference)
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assignLogicalWithSimpleRightOperandByte(assign.target, expr.left, expr.operator, expr.right)
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else if(expr.left is NumericLiteral || expr.left is IdentifierReference)
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assignLogicalWithSimpleRightOperandByte(assign.target, expr.right, expr.operator, expr.left)
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else {
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assignExpressionToRegister(expr.left, RegisterOrPair.A, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_B1", DataType.UBYTE, expr.definingSubroutine)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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when (expr.operator) {
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"&", "and" -> asmgen.out(" and P8ZP_SCRATCH_B1")
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"|", "or" -> asmgen.out(" ora P8ZP_SCRATCH_B1")
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"^", "xor" -> asmgen.out(" eor P8ZP_SCRATCH_B1")
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else -> throw AssemblyError("invalid operator")
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}
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assignRegisterByte(assign.target, CpuRegister.A)
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}
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assignRegisterByte(assign.target, CpuRegister.A)
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return true
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}
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if(expr.left.inferType(program).isWords && expr.right.inferType(program).isWords &&
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expr.left.isSimple && expr.right.isSimple) {
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// if(expr.right is NumericLiteral || expr.right is IdentifierReference) {
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// TODO("optimized code for logical with right number/variable arg (word)")
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// } else if(expr.left is NumericLiteral || expr.left is IdentifierReference) {
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// TODO("optimized code for logical with left number/variable arg (word)")
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// }
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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asmgen.saveRegisterStack(CpuRegister.Y, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_W1", DataType.UWORD, expr.definingSubroutine)
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when(expr.operator) {
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"&", "and" -> asmgen.out(" pla | and P8ZP_SCRATCH_W1+1 | tay | pla | and P8ZP_SCRATCH_W1")
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"|", "or" -> asmgen.out(" pla | ora P8ZP_SCRATCH_W1+1 | tay | pla | ora P8ZP_SCRATCH_W1")
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"^", "xor" -> asmgen.out(" pla | eor P8ZP_SCRATCH_W1+1 | tay | pla | eor P8ZP_SCRATCH_W1")
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else -> throw AssemblyError("invalid operator")
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if(expr.right is NumericLiteral || expr.right is IdentifierReference)
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assignLogicalWithSimpleRightOperandWord(assign.target, expr.left, expr.operator, expr.right)
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else if(expr.left is NumericLiteral || expr.left is IdentifierReference)
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assignLogicalWithSimpleRightOperandWord(assign.target, expr.right, expr.operator, expr.left)
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else {
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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asmgen.saveRegisterStack(CpuRegister.Y, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_W1", DataType.UWORD, expr.definingSubroutine)
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when (expr.operator) {
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"&", "and" -> asmgen.out(" pla | and P8ZP_SCRATCH_W1+1 | tay | pla | and P8ZP_SCRATCH_W1")
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"|", "or" -> asmgen.out(" pla | ora P8ZP_SCRATCH_W1+1 | tay | pla | ora P8ZP_SCRATCH_W1")
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"^", "xor" -> asmgen.out(" pla | eor P8ZP_SCRATCH_W1+1 | tay | pla | eor P8ZP_SCRATCH_W1")
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else -> throw AssemblyError("invalid operator")
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}
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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}
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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return true
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}
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return false
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@ -596,6 +597,48 @@ internal class AssignmentAsmGen(private val program: Program,
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return false
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}
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private fun assignLogicalWithSimpleRightOperandByte(target: AsmAssignTarget, left: Expression, operator: String, right: Expression) {
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assignExpressionToRegister(left, RegisterOrPair.A, false)
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val operand = when(right) {
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is NumericLiteral -> "#${right.number.toHex()}"
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is IdentifierReference -> asmgen.asmSymbolName(right)
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else -> throw AssemblyError("wrong right operand type")
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}
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when (operator) {
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"&", "and" -> asmgen.out(" and $operand")
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"|", "or" -> asmgen.out(" ora $operand")
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"^", "xor" -> asmgen.out(" eor $operand")
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else -> throw AssemblyError("invalid operator")
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}
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assignRegisterByte(target, CpuRegister.A)
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}
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private fun assignLogicalWithSimpleRightOperandWord(target: AsmAssignTarget, left: Expression, operator: String, right: Expression) {
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assignExpressionToRegister(left, RegisterOrPair.AY, false)
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when(right) {
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is NumericLiteral -> {
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val number = right.number.toHex()
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when (operator) {
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"&", "and" -> asmgen.out(" and #<$number | pha | tya | and #>$number | tay | pla")
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"|", "or" -> asmgen.out(" ora #<$number | pha | tya | ora #>$number | tay | pla")
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"^", "xor" -> asmgen.out(" eor #<$number | pha | tya | eor #>$number | tay | pla")
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else -> throw AssemblyError("invalid operator")
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}
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}
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is IdentifierReference -> {
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val name = asmgen.asmSymbolName(right)
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when (operator) {
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"&", "and" -> asmgen.out(" and $name | pha | tya | and $name+1 | tay | pla")
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"|", "or" -> asmgen.out(" ora $name | pha | tya | ora $name+1 | tay | pla")
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"^", "xor" -> asmgen.out(" eor $name | pha | tya | eor $name+1 | tay | pla")
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else -> throw AssemblyError("invalid operator")
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}
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}
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else -> throw AssemblyError("wrong right operand type")
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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}
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private fun attemptAssignToByteCompareZero(expr: BinaryExpression, assign: AsmAssignment): Boolean {
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when (expr.operator) {
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"==" -> {
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@ -3,8 +3,8 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- finish the logical expression optimizations set in TODO's in attemptAssignOptimizedBinexpr()
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- try more benchmarks from https://gglabs.us/node/2293
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- check that all examples still function correctly
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...
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@ -4,16 +4,15 @@
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main {
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sub start() {
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uword crc = $ffff
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txt.print_uwhex(crc | (crc & $8000), true)
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; if crc & $8000 ; msb(crc) & $80
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; txt.print("yes")
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; else
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; txt.print("fail!")
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;
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; if msb(crc) & $80
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; txt.print("yes")
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; else
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; txt.print("fail!")
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if crc & $8000 ; msb(crc) & $80
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txt.print("yes")
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else
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txt.print("fail!")
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if crc & $1234
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txt.print("yes")
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else
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txt.print("fail!")
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}
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; sub start2() {
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