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https://github.com/irmen/prog8.git
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implement missing operators in IR code gen
This commit is contained in:
Irmen de Jong
parent
2d85fd093e
commit
47d0f0ea40
@ -48,15 +48,22 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val value = assignment.value
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val vmDt = codeGen.irType(value.type)
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return when(assignment.operator) {
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"+" -> expressionEval.operatorPlusInplace(address, null, vmDt, value).chunks
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"-" -> expressionEval.operatorMinusInplace(address, null, vmDt, value).chunks
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"*" -> expressionEval.operatorMultiplyInplace(address, null, vmDt, value).chunks
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"/" -> expressionEval.operatorDivideInplace(address, null, vmDt, value.type in SignedDatatypes, value).chunks
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"|" -> expressionEval.operatorOrInplace(address, null, vmDt, value).chunks
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"&" -> expressionEval.operatorAndInplace(address, null, vmDt, value).chunks
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"^" -> expressionEval.operatorXorInplace(address, null, vmDt, value).chunks
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"<<" -> expressionEval.operatorShiftLeftInplace(address, null, vmDt, value).chunks
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">>" -> expressionEval.operatorShiftRightInplace(address, null, vmDt, value.type in SignedDatatypes, value).chunks
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"+" -> expressionEval.operatorPlusInplace(address, null, vmDt, value)
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"-" -> expressionEval.operatorMinusInplace(address, null, vmDt, value)
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"*" -> expressionEval.operatorMultiplyInplace(address, null, vmDt, value)
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"/" -> expressionEval.operatorDivideInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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"|" -> expressionEval.operatorOrInplace(address, null, vmDt, value)
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"&" -> expressionEval.operatorAndInplace(address, null, vmDt, value)
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"^" -> expressionEval.operatorXorInplace(address, null, vmDt, value)
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"<<" -> expressionEval.operatorShiftLeftInplace(address, null, vmDt, value)
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">>" -> expressionEval.operatorShiftRightInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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"%=" -> expressionEval.operatorModuloInplace(address, null, vmDt, value)
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"==" -> expressionEval.operatorEqualsInplace(address, null, vmDt, value)
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"!=" -> expressionEval.operatorNotEqualsInplace(address, null, vmDt, value)
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"<" -> expressionEval.operatorLessInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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">" -> expressionEval.operatorGreaterInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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"<=" -> expressionEval.operatorLessEqualInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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">=" -> expressionEval.operatorGreaterEqualInplace(address, null, vmDt, value.type in SignedDatatypes, value)
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in PrefixOperators -> inplacePrefix(assignment.operator, vmDt, address, null)
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else -> throw AssemblyError("invalid augmented assign operator ${assignment.operator}")
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@ -67,15 +74,22 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val value = assignment.value
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val valueVmDt = codeGen.irType(value.type)
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return when (assignment.operator) {
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"+=" -> expressionEval.operatorPlusInplace(null, symbol, valueVmDt, value).chunks
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"-=" -> expressionEval.operatorMinusInplace(null, symbol, valueVmDt, value).chunks
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"*=" -> expressionEval.operatorMultiplyInplace(null, symbol, valueVmDt, value).chunks
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"/=" -> expressionEval.operatorDivideInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value).chunks
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"|=" -> expressionEval.operatorOrInplace(null, symbol, valueVmDt, value).chunks
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"&=" -> expressionEval.operatorAndInplace(null, symbol, valueVmDt, value).chunks
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"^=" -> expressionEval.operatorXorInplace(null, symbol, valueVmDt, value).chunks
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"<<=" -> expressionEval.operatorShiftLeftInplace(null, symbol, valueVmDt, value).chunks
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">>=" -> expressionEval.operatorShiftRightInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value).chunks
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"+=" -> expressionEval.operatorPlusInplace(null, symbol, valueVmDt, value)
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"-=" -> expressionEval.operatorMinusInplace(null, symbol, valueVmDt, value)
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"*=" -> expressionEval.operatorMultiplyInplace(null, symbol, valueVmDt, value)
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"/=" -> expressionEval.operatorDivideInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"|=" -> expressionEval.operatorOrInplace(null, symbol, valueVmDt, value)
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"&=" -> expressionEval.operatorAndInplace(null, symbol, valueVmDt, value)
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"^=" -> expressionEval.operatorXorInplace(null, symbol, valueVmDt, value)
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"<<=" -> expressionEval.operatorShiftLeftInplace(null, symbol, valueVmDt, value)
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">>=" -> expressionEval.operatorShiftRightInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"%=" -> expressionEval.operatorModuloInplace(null, symbol, valueVmDt, value)
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"==" -> expressionEval.operatorEqualsInplace(null, symbol, valueVmDt, value)
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"!=" -> expressionEval.operatorNotEqualsInplace(null, symbol, valueVmDt, value)
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"<" -> expressionEval.operatorLessInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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">" -> expressionEval.operatorGreaterInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"<=" -> expressionEval.operatorLessEqualInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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">=" -> expressionEval.operatorGreaterEqualInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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in PrefixOperators -> inplacePrefix(assignment.operator, valueVmDt, null, symbol)
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else -> throw AssemblyError("invalid augmented assign operator ${assignment.operator}")
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}
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@ -84,8 +98,6 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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private fun fallbackAssign(origAssign: PtAugmentedAssign): IRCodeChunks {
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if (codeGen.options.slowCodegenWarnings)
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codeGen.errors.warn("indirect code for in-place assignment", origAssign.position)
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val normalAssign = PtAssignment(origAssign.position)
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normalAssign.add(origAssign.target)
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val value: PtExpression
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if(origAssign.operator in PrefixOperators) {
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value = PtPrefix(origAssign.operator, origAssign.value.type, origAssign.value.position)
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@ -93,7 +105,21 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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} else {
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require(origAssign.operator.endsWith('='))
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if(codeGen.options.useNewExprCode) {
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TODO("use something else than a BinExpr")
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// X += Y -> temp = X, temp += Y, X = temp
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val tempvarname = "some_random_tempvar" // TODO create proper tempvar
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val tempvar = PtIdentifier(tempvarname, origAssign.target.type, origAssign.position)
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val assign = PtAssignment(origAssign.position)
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val target = PtAssignTarget(origAssign.position)
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target.add(tempvar)
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assign.add(target)
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assign.add(origAssign.target.children.single())
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val augAssign = PtAugmentedAssign(origAssign.operator, origAssign.position)
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augAssign.add(target)
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augAssign.add(origAssign.value)
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val assignBack = PtAssignment(origAssign.position)
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assignBack.add(origAssign.target)
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assignBack.add(tempvar)
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return translateRegularAssign(assign) + translate(augAssign) + translateRegularAssign(assignBack)
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} else {
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value = PtBinaryExpression(origAssign.operator.dropLast(1), origAssign.value.type, origAssign.value.position)
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val left: PtExpression = origAssign.target.children.single() as PtExpression
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@ -101,6 +127,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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value.add(origAssign.value)
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}
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}
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val normalAssign = PtAssignment(origAssign.position)
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normalAssign.add(origAssign.target)
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normalAssign.add(value)
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return translateRegularAssign(normalAssign)
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}
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@ -262,18 +290,20 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int): Pair<IRCodeChunks, Int> {
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// returns the code to load the Index into the register, which is also return\ed.
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if(codeGen.options.useNewExprCode) {
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TODO("use aug assigns instead of BinExpr to calc proper array index")
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// return blah
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = if(itemsize==1) {
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expressionEval.translateExpression(array.index)
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} else {
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val mult : PtExpression
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if(codeGen.options.useNewExprCode) {
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TODO("use something else than a BinExpr")
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} else {
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mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
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mult.children += array.index
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mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
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}
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mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
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mult.children += array.index
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mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
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expressionEval.translateExpression(mult)
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}
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addToResult(result, tr, tr.resultReg, -1)
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@ -925,7 +925,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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internal fun operatorAndInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorAndInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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@ -934,10 +934,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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else
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IRInstruction(Opcode.ANDM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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,null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorOrInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorOrInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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@ -946,10 +946,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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else
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IRInstruction(Opcode.ORM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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, null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorDivideInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorDivideInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorRight = operand as? PtNumber
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if(vmDt==IRDataType.FLOAT) {
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@ -995,10 +995,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, ins, null)
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}
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorMultiplyInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorMultiplyInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorRight = operand as? PtNumber
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if(vmDt==IRDataType.FLOAT) {
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@ -1028,10 +1028,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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, null)
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}
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorMinusInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorMinusInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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if(vmDt==IRDataType.FLOAT) {
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if((operand as? PtNumber)?.number==1.0) {
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@ -1068,10 +1068,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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, null)
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}
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorPlusInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorPlusInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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if(vmDt==IRDataType.FLOAT) {
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if((operand as? PtNumber)?.number==1.0) {
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@ -1108,10 +1108,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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, null)
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}
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorShiftRightInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorShiftRightInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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if(codeGen.isOne(operand)) {
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val opc = if (signed) Opcode.ASRM else Opcode.LSRM
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@ -1130,10 +1130,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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IRInstruction(opc, vmDt, reg1 = tr.resultReg, labelSymbol = symbol)
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addInstr(result, ins, null)
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorShiftLeftInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorShiftLeftInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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if(codeGen.isOne(operand)){
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addInstr(result, if(knownAddress!=null)
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@ -1150,10 +1150,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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IRInstruction(Opcode.LSLNM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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,null)
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}
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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internal fun operatorXorInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): ExpressionCodeResult {
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internal fun operatorXorInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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@ -1162,9 +1162,198 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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else
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IRInstruction(Opcode.XORM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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,null)
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return ExpressionCodeResult(result, vmDt, -1, -1)
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return result
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}
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fun operatorModuloInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val resultReg = codeGen.registers.nextFree()
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if(operand is PtNumber) {
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val number = operand.number.toInt()
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if (knownAddress != null) {
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// @(address) = @(address) %= operand
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultReg, value = knownAddress)
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it += IRInstruction(Opcode.MOD, vmDt, reg1 = resultReg, value = number)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = resultReg, value = knownAddress)
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}
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} else {
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// symbol = symbol %= operand
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.MOD, vmDt, reg1 = resultReg, value = number)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = resultReg, labelSymbol = symbol)
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}
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}
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} else {
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val tr = translateExpression(operand)
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result += tr.chunks
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if (knownAddress != null) {
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// @(address) = @(address) %= operand
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultReg, value = knownAddress)
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it += IRInstruction(Opcode.MODR, vmDt, reg1 = resultReg, reg2 = tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = resultReg, value = knownAddress)
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}
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} else {
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// symbol = symbol %= operand
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.MODR, vmDt, reg1 = resultReg, reg2 = tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = resultReg, labelSymbol = symbol)
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}
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}
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}
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return result
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}
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fun operatorEqualsInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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if(knownAddress!=null) {
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// @(address) = @(address) == operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
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}
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} else {
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// symbol = symbol == operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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}
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}
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return result
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}
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fun operatorNotEqualsInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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if(knownAddress!=null) {
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// @(address) = @(address) != operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
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}
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} else {
|
||||
// symbol = symbol != operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
|
||||
it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
|
||||
}
|
||||
}
|
||||
return result
|
||||
}
|
||||
|
||||
fun operatorGreaterInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
val tr = translateExpression(operand)
|
||||
addToResult(result, tr, tr.resultReg, -1)
|
||||
val opcode = if(signed) Opcode.SGTS else Opcode.SGT
|
||||
if(knownAddress!=null) {
|
||||
// @(address) = @(address) > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
|
||||
}
|
||||
} else {
|
||||
// symbol = symbol > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
|
||||
}
|
||||
}
|
||||
return result
|
||||
}
|
||||
|
||||
fun operatorLessInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
val tr = translateExpression(operand)
|
||||
addToResult(result, tr, tr.resultReg, -1)
|
||||
val opcode = if(signed) Opcode.SLTS else Opcode.SLT
|
||||
if(knownAddress!=null) {
|
||||
// @(address) = @(address) < operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
|
||||
}
|
||||
} else {
|
||||
// symbol = symbol < operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
|
||||
}
|
||||
}
|
||||
return result
|
||||
}
|
||||
|
||||
fun operatorGreaterEqualInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
val tr = translateExpression(operand)
|
||||
addToResult(result, tr, tr.resultReg, -1)
|
||||
val opcode = if(signed) Opcode.SGES else Opcode.SGE
|
||||
if(knownAddress!=null) {
|
||||
// @(address) = @(address) > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
|
||||
}
|
||||
} else {
|
||||
// symbol = symbol > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
|
||||
}
|
||||
}
|
||||
return result
|
||||
}
|
||||
|
||||
fun operatorLessEqualInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
val tr = translateExpression(operand)
|
||||
addToResult(result, tr, tr.resultReg, -1)
|
||||
val opcode = if(signed) Opcode.SLES else Opcode.SLE
|
||||
if(knownAddress!=null) {
|
||||
// @(address) = @(address) > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
|
||||
}
|
||||
} else {
|
||||
// symbol = symbol > operand
|
||||
val valueReg = codeGen.registers.nextFree()
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
|
||||
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
|
||||
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
|
||||
}
|
||||
}
|
||||
return result
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -912,67 +912,83 @@ class IRCodeGen(
|
||||
}
|
||||
}
|
||||
else -> {
|
||||
throw AssemblyError("weird condition node: $condition")
|
||||
// if X --> meaning: if X!=0
|
||||
require(options.useNewExprCode)
|
||||
val irDt = irType(condition.type)
|
||||
val signed = condition.type in SignedDatatypes
|
||||
return if(goto!=null && ifElse.elseScope.children.isEmpty()) {
|
||||
translateIfFollowedByJustGoto(ifElse, goto, irDt, signed)
|
||||
} else {
|
||||
translateIfElseNonZeroComparison(ifElse, irDt, signed)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
private fun translateIfFollowedByJustGoto(ifElse: PtIfElse, goto: PtJump, irDtLeft: IRDataType, signed: Boolean): MutableList<IRCodeChunkBase> {
|
||||
val condition = ifElse.condition as PtBinaryExpression
|
||||
val conditionBinExpr = ifElse.condition as? PtBinaryExpression
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
if (irDtLeft == IRDataType.FLOAT) {
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
val compResultReg = registers.nextFree()
|
||||
it += IRInstruction(
|
||||
Opcode.FCOMP,
|
||||
IRDataType.FLOAT,
|
||||
reg1 = compResultReg,
|
||||
fpReg1 = leftTr.resultFpReg,
|
||||
fpReg2 = rightTr.resultFpReg
|
||||
)
|
||||
val gotoOpcode = when (condition.operator) {
|
||||
"==" -> Opcode.BZ
|
||||
"!=" -> Opcode.BNZ
|
||||
"<" -> Opcode.BLEZS
|
||||
">" -> Opcode.BGEZS
|
||||
"<=" -> Opcode.BLZS
|
||||
">=" -> Opcode.BGZS
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
it += if (goto.address != null)
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
value = goto.address?.toInt()
|
||||
)
|
||||
else if (goto.generatedLabel != null)
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
labelSymbol = goto.generatedLabel
|
||||
)
|
||||
else
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
labelSymbol = goto.identifier!!.name
|
||||
)
|
||||
}
|
||||
if(conditionBinExpr==null) {
|
||||
if(irDtLeft==IRDataType.FLOAT)
|
||||
throw AssemblyError("condition value should not be float")
|
||||
ifNonZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
|
||||
return result
|
||||
} else {
|
||||
val rightConst = condition.right.asConstInteger()
|
||||
return if (rightConst == 0)
|
||||
ifZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
|
||||
else {
|
||||
ifNonZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
|
||||
if (irDtLeft == IRDataType.FLOAT) {
|
||||
val leftTr = expressionEval.translateExpression(conditionBinExpr.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(conditionBinExpr.right)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
val compResultReg = registers.nextFree()
|
||||
it += IRInstruction(
|
||||
Opcode.FCOMP,
|
||||
IRDataType.FLOAT,
|
||||
reg1 = compResultReg,
|
||||
fpReg1 = leftTr.resultFpReg,
|
||||
fpReg2 = rightTr.resultFpReg
|
||||
)
|
||||
val gotoOpcode = when (conditionBinExpr.operator) {
|
||||
"==" -> Opcode.BZ
|
||||
"!=" -> Opcode.BNZ
|
||||
"<" -> Opcode.BLEZS
|
||||
">" -> Opcode.BGEZS
|
||||
"<=" -> Opcode.BLZS
|
||||
">=" -> Opcode.BGZS
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
it += if (goto.address != null)
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
value = goto.address?.toInt()
|
||||
)
|
||||
else if (goto.generatedLabel != null)
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
labelSymbol = goto.generatedLabel
|
||||
)
|
||||
else
|
||||
IRInstruction(
|
||||
gotoOpcode,
|
||||
IRDataType.BYTE,
|
||||
reg1 = compResultReg,
|
||||
labelSymbol = goto.identifier!!.name
|
||||
)
|
||||
}
|
||||
return result
|
||||
} else {
|
||||
val rightConst = conditionBinExpr.right.asConstInteger()
|
||||
if (rightConst == 0)
|
||||
ifZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
|
||||
else {
|
||||
ifNonZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
|
||||
}
|
||||
return result
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -983,7 +999,7 @@ class IRCodeGen(
|
||||
signed: Boolean,
|
||||
irDtLeft: IRDataType,
|
||||
goto: PtJump
|
||||
): MutableList<IRCodeChunkBase> {
|
||||
) {
|
||||
val condition = ifElse.condition as PtBinaryExpression
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
@ -1002,7 +1018,6 @@ class IRCodeGen(
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, labelSymbol = goto.generatedLabel), null)
|
||||
else
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, labelSymbol = goto.identifier!!.name), null)
|
||||
return result
|
||||
}
|
||||
|
||||
private fun ifNonZeroIntThenJump(
|
||||
@ -1011,57 +1026,67 @@ class IRCodeGen(
|
||||
signed: Boolean,
|
||||
irDtLeft: IRDataType,
|
||||
goto: PtJump
|
||||
): MutableList<IRCodeChunkBase> {
|
||||
val condition = ifElse.condition as PtBinaryExpression
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
val opcode: Opcode
|
||||
val firstReg: Int
|
||||
val secondReg: Int
|
||||
when (condition.operator) {
|
||||
"==" -> {
|
||||
opcode = Opcode.BEQ
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
) {
|
||||
val conditionBinExpr = ifElse.condition as? PtBinaryExpression
|
||||
if(conditionBinExpr==null) {
|
||||
val tr = expressionEval.translateExpression(ifElse.condition)
|
||||
result += tr.chunks
|
||||
if (goto.address != null)
|
||||
addInstr(result, IRInstruction(Opcode.BNZ, irDtLeft, reg1 = tr.resultReg, value = goto.address?.toInt()), null)
|
||||
else if (goto.generatedLabel != null)
|
||||
addInstr(result, IRInstruction(Opcode.BNZ, irDtLeft, reg1 = tr.resultReg, labelSymbol = goto.generatedLabel), null)
|
||||
else
|
||||
addInstr(result, IRInstruction(Opcode.BNZ, irDtLeft, reg1 = tr.resultReg, labelSymbol = goto.identifier!!.name), null)
|
||||
} else {
|
||||
val leftTr = expressionEval.translateExpression(conditionBinExpr.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(conditionBinExpr.right)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
val opcode: Opcode
|
||||
val firstReg: Int
|
||||
val secondReg: Int
|
||||
when (conditionBinExpr.operator) {
|
||||
"==" -> {
|
||||
opcode = Opcode.BEQ
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"!=" -> {
|
||||
opcode = Opcode.BNE
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<" -> {
|
||||
// swapped '>'
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// swapped '>='
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">=" -> {
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
"!=" -> {
|
||||
opcode = Opcode.BNE
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<" -> {
|
||||
// swapped '>'
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// swapped '>='
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">=" -> {
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
if (goto.address != null)
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, value = goto.address?.toInt()), null)
|
||||
else if (goto.generatedLabel != null)
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.generatedLabel), null)
|
||||
else
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.identifier!!.name), null)
|
||||
}
|
||||
if (goto.address != null)
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, value = goto.address?.toInt()), null)
|
||||
else if (goto.generatedLabel != null)
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.generatedLabel), null)
|
||||
else
|
||||
addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.identifier!!.name), null)
|
||||
return result
|
||||
}
|
||||
|
||||
private fun translateIfElseZeroComparison(ifElse: PtIfElse, irDtLeft: IRDataType, signed: Boolean): IRCodeChunks {
|
||||
@ -1131,106 +1156,160 @@ class IRCodeGen(
|
||||
val elseBranchFirstReg: Int
|
||||
val elseBranchSecondReg: Int
|
||||
val branchDt: IRDataType
|
||||
val condition = ifElse.condition as PtBinaryExpression
|
||||
if(irDtLeft==IRDataType.FLOAT) {
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
val compResultReg = registers.nextFree()
|
||||
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
|
||||
val elseBranch = when (condition.operator) {
|
||||
"==" -> Opcode.BNZ
|
||||
"!=" -> Opcode.BZ
|
||||
"<" -> Opcode.BGEZS
|
||||
">" -> Opcode.BLEZS
|
||||
"<=" -> Opcode.BGZS
|
||||
">=" -> Opcode.BLZS
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
val condition = ifElse.condition as? PtBinaryExpression
|
||||
if(condition==null) {
|
||||
if(irDtLeft==IRDataType.FLOAT)
|
||||
throw AssemblyError("condition value should not be float")
|
||||
val tr = expressionEval.translateExpression(ifElse.condition)
|
||||
result += tr.chunks
|
||||
if(ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(result, IRInstruction(elseBranch, IRDataType.BYTE, reg1=compResultReg, labelSymbol = elseLabel), null)
|
||||
addInstr(result, IRInstruction(Opcode.BZ, irDtLeft, reg1=tr.resultReg, labelSymbol = elseLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(result, IRInstruction(elseBranch, IRDataType.BYTE, reg1=compResultReg, labelSymbol = afterIfLabel), null)
|
||||
addInstr(result, IRInstruction(Opcode.BZ, irDtLeft, reg1=tr.resultReg, labelSymbol = afterIfLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
return result
|
||||
} else {
|
||||
// integer comparisons
|
||||
branchDt = irDtLeft
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
when (condition.operator) {
|
||||
"==" -> {
|
||||
elseBranchOpcode = Opcode.BNE
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
if (irDtLeft == IRDataType.FLOAT) {
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
val compResultReg = registers.nextFree()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(
|
||||
Opcode.FCOMP,
|
||||
IRDataType.FLOAT,
|
||||
reg1 = compResultReg,
|
||||
fpReg1 = leftTr.resultFpReg,
|
||||
fpReg2 = rightTr.resultFpReg
|
||||
),
|
||||
null
|
||||
)
|
||||
val elseBranch = when (condition.operator) {
|
||||
"==" -> Opcode.BNZ
|
||||
"!=" -> Opcode.BZ
|
||||
"<" -> Opcode.BGEZS
|
||||
">" -> Opcode.BLEZS
|
||||
"<=" -> Opcode.BGZS
|
||||
">=" -> Opcode.BLZS
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
"!=" -> {
|
||||
elseBranchOpcode = Opcode.BEQ
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
if (ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = elseLabel),
|
||||
null
|
||||
)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = afterIfLabel),
|
||||
null
|
||||
)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
"<" -> {
|
||||
// else part when left >= right
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
// else part when left <= right --> right >= left
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// else part when left > right
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
">=" -> {
|
||||
// else part when left < right --> right > left
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
if(ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(result, IRInstruction(elseBranchOpcode, branchDt,
|
||||
reg1=elseBranchFirstReg, reg2=elseBranchSecondReg,
|
||||
labelSymbol = elseLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(result, IRInstruction(elseBranchOpcode, branchDt,
|
||||
reg1=elseBranchFirstReg, reg2=elseBranchSecondReg,
|
||||
labelSymbol = afterIfLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
}
|
||||
// integer comparisons
|
||||
branchDt = irDtLeft
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
when (condition.operator) {
|
||||
"==" -> {
|
||||
elseBranchOpcode = Opcode.BNE
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
|
||||
return result
|
||||
"!=" -> {
|
||||
elseBranchOpcode = Opcode.BEQ
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
|
||||
"<" -> {
|
||||
// else part when left >= right
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
|
||||
">" -> {
|
||||
// else part when left <= right --> right >= left
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
|
||||
"<=" -> {
|
||||
// else part when left > right
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
|
||||
">=" -> {
|
||||
// else part when left < right --> right > left
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
if (ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg,
|
||||
labelSymbol = elseLabel
|
||||
), null
|
||||
)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg,
|
||||
labelSymbol = afterIfLabel
|
||||
), null
|
||||
)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
}
|
||||
|
||||
return result
|
||||
}
|
||||
}
|
||||
|
||||
private fun translate(postIncrDecr: PtPostIncrDecr): IRCodeChunks {
|
||||
|
||||
@ -4,6 +4,9 @@ TODO
|
||||
|
||||
For next minor release
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
newexpr: fix fallbackAssign() and loadIndexReg()
|
||||
|
||||
...
|
||||
|
||||
|
||||
|
||||
@ -1,9 +1,16 @@
|
||||
%import textio
|
||||
%import floats
|
||||
%zeropage basicsafe
|
||||
|
||||
|
||||
main {
|
||||
sub start() {
|
||||
ubyte xx=100
|
||||
ubyte yy=21
|
||||
|
||||
xx %= yy
|
||||
txt.print_ub(xx)
|
||||
txt.nl()
|
||||
|
||||
ubyte ub1 = 100
|
||||
ubyte ub2 = 13
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user