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IR: support %align in code chunks, and load/store FAC0/FAC1
This commit is contained in:
Irmen de Jong
parent
c86c0912f8
commit
49959af752
@ -627,7 +627,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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RegisterOrPair.AX -> addInstr(result, IRInstruction(Opcode.STOREHAX, IRDataType.WORD, reg1=tr.resultReg), null)
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RegisterOrPair.AY -> addInstr(result, IRInstruction(Opcode.STOREHAY, IRDataType.WORD, reg1=tr.resultReg), null)
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RegisterOrPair.XY -> addInstr(result, IRInstruction(Opcode.STOREHXY, IRDataType.WORD, reg1=tr.resultReg), null)
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> TODO("floating point register parameters not supported")
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RegisterOrPair.FAC1 -> addInstr(result, IRInstruction(Opcode.STOREHFACZERO, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
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RegisterOrPair.FAC2 -> addInstr(result, IRInstruction(Opcode.STOREHFACONE, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
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in Cx16VirtualRegisters -> {
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addInstr(result, IRInstruction(Opcode.STOREM, paramDt, reg1=tr.resultReg, labelSymbol = "cx16.${parameter.register.registerOrPair.toString().lowercase()}"), null)
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}
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@ -231,7 +231,11 @@ class IRCodeGen(
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chunk += IRInstruction(Opcode.BREAKPOINT)
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listOf(chunk)
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}
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is PtAlign -> TODO("ir support for inline %align")
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is PtAlign -> {
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val chunk = IRCodeChunk(null, null)
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chunk += IRInstruction(Opcode.ALIGN, immediate = node.align.toInt())
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listOf(chunk)
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}
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is PtConditionalBranch -> translate(node)
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is PtInlineAssembly -> listOf(IRInlineAsmChunk(null, node.assembly, node.isIR, null))
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is PtIncludeBinary -> listOf(IRInlineBinaryChunk(null, readBinaryData(node), null))
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@ -58,9 +58,7 @@ IR/VM
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- fix TODO("IR rol/ror on split words array")
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- fix "<< in array" / ">> in array"
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- implement missing operators in AssignmentGen (array shifts etc)
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- support %align on code chunks
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- fix call() return value handling
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- fix float register parameters (FAC1,FAC2) for extsubs, search for TODO("floating point register parameters not supported")
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- proper code gen for the CALLI instruction and that it (optionally) returns a word value that needs to be assigned to a reg
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- make it possible to jump and branch to a computed address (expression) in all cases, see TODO("JUMP to expression address"
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- idea: (but LLVM IR simply keeps the variables, so not a good idea then?...): replace all scalar variables by an allocated register. Keep a table of the variable to register mapping (including the datatype)
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@ -47,6 +47,8 @@ loadhy reg1 - load cpu hardware register Y into reg1.b
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loadhax reg1 - load cpu hardware register pair AX into reg1.w
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loadhay reg1 - load cpu hardware register pair AY into reg1.w
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loadhxy reg1 - load cpu hardware register pair XY into reg1.w
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loadfaczero fpreg1 - load "cpu hardware register" fac0 into freg1.f
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loadfacone fpreg1 - load "cpu hardware register" fac1 into freg1.f
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storem reg1, address - store reg1 at memory address
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storei reg1, reg2 - store reg1 at memory indirect, memory pointed to by reg2
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storex reg1, reg2, address - store reg1 at memory address, indexed by value in reg2 (only the lsb part used for indexing)
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@ -60,6 +62,8 @@ storehy reg1 - store reg1.b into cpu hardware register
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storehax reg1 - store reg1.w into cpu hardware register pair AX
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storehay reg1 - store reg1.w into cpu hardware register pair AY
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storehxy reg1 - store reg1.w into cpu hardware register pair XY
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storehfaczero fpreg1 - store fpreg1.f into "cpu register" fac0
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storehfacone fpreg1 - store fpreg1.f into "cpu register" fac1
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CONTROL FLOW
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@ -246,6 +250,7 @@ cli - clear interrupt disable flag
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sei - set interrupt disable flag
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nop - do nothing
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breakpoint - trigger a breakpoint
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align alignmentvalue - represents a memory alignment directive
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msig [b, w] reg1, reg2 - reg1 becomes the most significant byte (or word) of the word (or int) in reg2 (.w not yet implemented; requires 32 bits regs)
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concat [b, w] reg1, reg2, reg3 - reg1.w = 'concatenate' two registers: lsb/lsw of reg2 (as msb) and lsb/lsw of reg3 (as lsb) into word or int (int not yet implemented; requires 32bits regs)
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push [b, w, f] reg1 - push value in reg1 on the stack
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@ -268,6 +273,8 @@ enum class Opcode {
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LOADHAX,
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LOADHAY,
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LOADHXY,
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LOADHFACZERO,
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LOADHFACONE,
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STOREM,
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STOREI,
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STOREX,
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@ -281,6 +288,8 @@ enum class Opcode {
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STOREHAX,
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STOREHAY,
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STOREHXY,
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STOREHFACZERO,
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STOREHFACONE,
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JUMP,
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JUMPI,
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@ -423,7 +432,8 @@ enum class Opcode {
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POPST,
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MSIG,
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CONCAT,
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BREAKPOINT
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BREAKPOINT,
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ALIGN
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}
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val OpcodesThatJump = arrayOf(
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@ -630,6 +640,8 @@ val instructionFormats = mutableMapOf(
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Opcode.LOADHAX to InstructionFormat.from("W,>r1"),
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Opcode.LOADHAY to InstructionFormat.from("W,>r1"),
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Opcode.LOADHXY to InstructionFormat.from("W,>r1"),
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Opcode.LOADHFACZERO to InstructionFormat.from("F,>fr1"),
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Opcode.LOADHFACONE to InstructionFormat.from("F,>fr1"),
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Opcode.STOREM to InstructionFormat.from("BW,<r1,>a | F,<fr1,>a"),
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Opcode.STOREI to InstructionFormat.from("BW,<r1,<r2 | F,<fr1,<r1"),
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Opcode.STOREX to InstructionFormat.from("BW,<r1,<r2,>a | F,<fr1,<r1,>a"),
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@ -644,6 +656,8 @@ val instructionFormats = mutableMapOf(
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Opcode.STOREHAX to InstructionFormat.from("W,<r1"),
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Opcode.STOREHAY to InstructionFormat.from("W,<r1"),
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Opcode.STOREHXY to InstructionFormat.from("W,<r1"),
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Opcode.STOREHFACZERO to InstructionFormat.from("F,<fr1"),
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Opcode.STOREHFACONE to InstructionFormat.from("F,<fr1"),
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Opcode.JUMP to InstructionFormat.from("N,<a"),
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Opcode.JUMPI to InstructionFormat.from("N,<r1"),
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Opcode.PREPARECALL to InstructionFormat.from("N,<i"),
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@ -783,6 +797,7 @@ val instructionFormats = mutableMapOf(
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Opcode.CLI to InstructionFormat.from("N"),
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Opcode.SEI to InstructionFormat.from("N"),
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Opcode.BREAKPOINT to InstructionFormat.from("N"),
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Opcode.ALIGN to InstructionFormat.from("N,<i"),
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)
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@ -256,7 +256,7 @@ private class ParsedCall(
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private fun parseCall(rest: String): ParsedCall {
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fun parseRegspec(reg: String): FunctionCallArgs.RegSpec {
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val pattern = Regex("f?r([0-9]+)\\.(.)(@.{1,2})?$")
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val pattern = Regex("f?r([0-9]+)\\.(.)(@.{1,4})?$")
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val match = pattern.matchEntire(reg) ?: throw IRParseException("invalid regspec $reg")
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val num = match.groups[1]!!.value.toInt()
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val type = when(match.groups[2]!!.value) {
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@ -191,7 +191,9 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.LOADHY,
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Opcode.LOADHAX,
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Opcode.LOADHAY,
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Opcode.LOADHXY -> throw IllegalArgumentException("VM cannot access actual CPU hardware register")
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Opcode.LOADHXY,
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Opcode.LOADHFACZERO,
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Opcode.LOADHFACONE -> throw IllegalArgumentException("VM cannot access actual CPU hardware register")
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Opcode.STOREM -> InsSTOREM(ins)
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Opcode.STOREX -> InsSTOREX(ins)
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Opcode.STOREIX -> InsSTOREIX(ins)
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@ -204,7 +206,9 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.STOREHY,
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Opcode.STOREHAX,
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Opcode.STOREHAY,
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Opcode.STOREHXY -> throw IllegalArgumentException("VM cannot access actual CPU hardware register")
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Opcode.STOREHXY,
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Opcode.STOREHFACZERO,
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Opcode.STOREHFACONE-> throw IllegalArgumentException("VM cannot access actual CPU hardware register")
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Opcode.JUMP -> InsJUMP(ins)
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Opcode.JUMPI -> InsJUMPI(ins)
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Opcode.PREPARECALL -> nextPc()
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@ -341,6 +345,7 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.FFLOOR -> InsFFLOOR(ins)
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Opcode.FCEIL -> InsFCEIL(ins)
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Opcode.FCOMP -> InsFCOMP(ins)
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Opcode.ALIGN -> nextPc() // actual alignment ignored in the VM
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else -> throw IllegalArgumentException("invalid opcode ${ins.opcode}")
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}
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