mirror of
https://github.com/irmen/prog8.git
synced 2024-09-10 09:54:32 +00:00
vm: limit float instructions to just 2 register args
This commit is contained in:
parent
74c05d00a9
commit
4be7bc8323
@ -80,12 +80,11 @@ internal class VmCodeInstruction(
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reg3: Int?=null, // 0-$ffff
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reg3: Int?=null, // 0-$ffff
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fpReg1: Int?=null, // 0-$ffff
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fpReg1: Int?=null, // 0-$ffff
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fpReg2: Int?=null, // 0-$ffff
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fpReg2: Int?=null, // 0-$ffff
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fpReg3: Int?=null, // 0-$ffff
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value: Int?=null, // 0-$ffff
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value: Int?=null, // 0-$ffff
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fpValue: Float?=null,
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fpValue: Float?=null,
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symbol: List<String>?=null // alternative to value
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symbol: List<String>?=null // alternative to value
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): VmCodeLine() {
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): VmCodeLine() {
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val ins = Instruction(opcode, type, reg1, reg2, reg3, fpReg1, fpReg2, fpReg3, value, fpValue, symbol)
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val ins = Instruction(opcode, type, reg1, reg2, reg3, fpReg1, fpReg2, value, fpValue, symbol)
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init {
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init {
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if(reg1!=null && (reg1<0 || reg1>65536))
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if(reg1!=null && (reg1<0 || reg1>65536))
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@ -98,8 +97,6 @@ internal class VmCodeInstruction(
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throw IllegalArgumentException("fpReg1 out of bounds")
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throw IllegalArgumentException("fpReg1 out of bounds")
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if(fpReg2!=null && (fpReg2<0 || fpReg2>65536))
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if(fpReg2!=null && (fpReg2<0 || fpReg2>65536))
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throw IllegalArgumentException("fpReg2 out of bounds")
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throw IllegalArgumentException("fpReg2 out of bounds")
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if(fpReg3!=null && (fpReg3<0 || fpReg3>65536))
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throw IllegalArgumentException("fpReg3 out of bounds")
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if(value!=null && opcode !in OpcodesWithAddress) {
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if(value!=null && opcode !in OpcodesWithAddress) {
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when (type) {
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when (type) {
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@ -389,7 +389,7 @@ class CodeGen(internal val program: PtProgram,
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} else {
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} else {
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val factorReg = vmRegisters.nextFreeFloat()
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val factorReg = vmRegisters.nextFreeFloat()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.FLOAT, fpReg1=factorReg, fpValue = factor)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.FLOAT, fpReg1=factorReg, fpValue = factor)
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code += VmCodeInstruction(Opcode.MUL, VmDataType.FLOAT, fpReg1 = fpReg, fpReg2 = fpReg, fpReg3 = factorReg)
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code += VmCodeInstruction(Opcode.MUL, VmDataType.FLOAT, fpReg1 = fpReg, fpReg2 = factorReg)
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}
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}
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return code
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return code
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}
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}
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@ -432,7 +432,7 @@ class CodeGen(internal val program: PtProgram,
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} else {
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} else {
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val factorReg = vmRegisters.nextFreeFloat()
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val factorReg = vmRegisters.nextFreeFloat()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.FLOAT, fpReg1=factorReg, fpValue = factor)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.FLOAT, fpReg1=factorReg, fpValue = factor)
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code += VmCodeInstruction(Opcode.DIV, VmDataType.FLOAT, fpReg1 = fpReg, fpReg2 = fpReg, fpReg3 = factorReg)
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code += VmCodeInstruction(Opcode.DIV, VmDataType.FLOAT, fpReg1 = fpReg, fpReg2 = factorReg)
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}
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}
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return code
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return code
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}
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}
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@ -487,7 +487,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += VmCodeInstruction(Opcode.DIV, vmDt, fpReg1 = resultFpRegister, fpReg2=resultFpRegister, fpReg3=rightResultFpReg)
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code += VmCodeInstruction(Opcode.DIV, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg)
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}
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}
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} else {
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} else {
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if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) {
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if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) {
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@ -521,7 +521,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += VmCodeInstruction(Opcode.MUL, vmDt, fpReg1 = resultFpRegister, fpReg2 = resultFpRegister, fpReg3 = rightResultFpReg)
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code += VmCodeInstruction(Opcode.MUL, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg)
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}
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}
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} else {
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} else {
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if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) {
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if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) {
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@ -553,7 +553,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += VmCodeInstruction(Opcode.SUB, vmDt, fpReg1=resultFpRegister, fpReg2=resultFpRegister, fpReg3=rightResultFpReg)
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code += VmCodeInstruction(Opcode.SUB, vmDt, fpReg1=resultFpRegister, fpReg2=rightResultFpReg)
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}
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}
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} else {
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} else {
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if((binExpr.right as? PtNumber)?.number==1.0) {
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if((binExpr.right as? PtNumber)?.number==1.0) {
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@ -585,7 +585,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightResultFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.left, -1, resultFpRegister)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += translateExpression(binExpr.right, -1, rightResultFpReg)
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code += VmCodeInstruction(Opcode.ADD, vmDt, fpReg1=resultFpRegister, fpReg2=resultFpRegister, fpReg3=rightResultFpReg)
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code += VmCodeInstruction(Opcode.ADD, vmDt, fpReg1=resultFpRegister, fpReg2=rightResultFpReg)
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}
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}
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} else {
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} else {
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if((binExpr.left as? PtNumber)?.number==1.0) {
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if((binExpr.left as? PtNumber)?.number==1.0) {
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@ -22,7 +22,7 @@ sub pow(float value, float power) -> float {
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%asm {{
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%asm {{
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loadm.f fr0,{floats.pow.value}
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loadm.f fr0,{floats.pow.value}
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loadm.f fr1,{floats.pow.power}
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loadm.f fr1,{floats.pow.power}
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fpow.f fr0,fr0,fr1
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fpow.f fr0,fr1
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return
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return
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}}
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}}
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}
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}
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@ -27,6 +27,7 @@ main {
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float fl1 = 1.1
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float fl1 = 1.1
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float fl2 = 2.2
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float fl2 = 2.2
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floats.print_f(floats.pow(fl1,fl2))
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if fl1==fl2
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if fl1==fl2
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txt.print("equals!?\n")
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txt.print("equals!?\n")
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@ -157,6 +157,10 @@ class Assembler {
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fpReg2 = fpReg3
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fpReg2 = fpReg3
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fpReg3 = null
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fpReg3 = null
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}
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}
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if(fpReg3!=null)
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throw IllegalArgumentException("too many fpreg arguments $line")
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// TODO also check reg3
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if(type!=null && type !in formats)
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if(type!=null && type !in formats)
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throw IllegalArgumentException("invalid type code for $line")
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throw IllegalArgumentException("invalid type code for $line")
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@ -196,7 +200,7 @@ class Assembler {
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if(format.fpValue)
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if(format.fpValue)
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floatValue = value!!
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floatValue = value!!
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program.add(Instruction(opcode, type, reg1, reg2, reg3, fpReg1, fpReg2, fpReg3, value = intValue, fpValue = floatValue))
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program.add(Instruction(opcode, type, reg1, reg2, reg3, fpReg1, fpReg2, value = intValue, fpValue = floatValue))
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}
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}
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}
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}
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@ -138,7 +138,7 @@ ftoub reg1, fpreg1 - reg1 = fpreg1 as unsigned byte
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ftosb reg1, fpreg1 - reg1 = fpreg1 as signed byte
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ftosb reg1, fpreg1 - reg1 = fpreg1 as signed byte
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ftouw reg1, fpreg1 - reg1 = fpreg1 as unsigned word
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ftouw reg1, fpreg1 - reg1 = fpreg1 as unsigned word
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ftosw reg1, fpreg1 - reg1 = fpreg1 as signed word
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ftosw reg1, fpreg1 - reg1 = fpreg1 as signed word
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fpow fpreg1, fpreg2, fpreg3 - fpreg1 = fpreg2 to the power of fpreg3
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fpow fpreg1, fpreg2 - fpreg1 = fpreg1 to the power of fpreg2
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fabs fpreg1, fpreg2 - fpreg1 = abs(fpreg2)
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fabs fpreg1, fpreg2 - fpreg1 = abs(fpreg2)
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fcomp reg1, fpreg1, fpreg2 - reg1 = result of comparison of fpreg1 and fpreg2: 0=equal, 1=fpreg1 is greater, -1=fpreg1 is smaller
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fcomp reg1, fpreg1, fpreg2 - reg1 = result of comparison of fpreg1 and fpreg2: 0=equal, 1=fpreg1 is greater, -1=fpreg1 is smaller
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@ -292,7 +292,6 @@ data class Instruction(
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val reg3: Int?=null, // 0-$ffff
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val reg3: Int?=null, // 0-$ffff
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val fpReg1: Int?=null, // 0-$ffff
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val fpReg1: Int?=null, // 0-$ffff
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val fpReg2: Int?=null, // 0-$ffff
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val fpReg2: Int?=null, // 0-$ffff
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val fpReg3: Int?=null, // 0-$ffff
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val value: Int?=null, // 0-$ffff
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val value: Int?=null, // 0-$ffff
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val fpValue: Float?=null,
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val fpValue: Float?=null,
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val symbol: List<String>?=null // alternative to value
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val symbol: List<String>?=null // alternative to value
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@ -308,9 +307,7 @@ data class Instruction(
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format.reg3 && reg3==null)
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format.reg3 && reg3==null)
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throw IllegalArgumentException("missing a register (int)")
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throw IllegalArgumentException("missing a register (int)")
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if(format.fpReg1 && fpReg1==null ||
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if(format.fpReg1 && fpReg1==null || format.fpReg2 && fpReg2==null)
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format.fpReg2 && fpReg2==null ||
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format.fpReg3 && fpReg3==null)
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throw IllegalArgumentException("missing a register (float)")
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throw IllegalArgumentException("missing a register (float)")
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if(!format.reg1 && reg1!=null ||
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if(!format.reg1 && reg1!=null ||
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@ -318,9 +315,7 @@ data class Instruction(
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!format.reg3 && reg3!=null)
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!format.reg3 && reg3!=null)
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throw IllegalArgumentException("too many registers (int)")
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throw IllegalArgumentException("too many registers (int)")
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if(!format.fpReg1 && fpReg1!=null ||
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if(!format.fpReg1 && fpReg1!=null || !format.fpReg2 && fpReg2!=null)
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!format.fpReg2 && fpReg2!=null ||
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!format.fpReg3 && fpReg3!=null)
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throw IllegalArgumentException("too many registers (float)")
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throw IllegalArgumentException("too many registers (float)")
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if (type==VmDataType.FLOAT) {
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if (type==VmDataType.FLOAT) {
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@ -329,7 +324,7 @@ data class Instruction(
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} else {
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} else {
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if(format.value && (value==null && symbol==null))
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if(format.value && (value==null && symbol==null))
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throw IllegalArgumentException("$opcode: missing a value or symbol")
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throw IllegalArgumentException("$opcode: missing a value or symbol")
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if (fpReg1 != null || fpReg2 != null || fpReg3 != null)
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if (fpReg1 != null || fpReg2 != null)
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throw java.lang.IllegalArgumentException("$opcode: integer point instruction can't use floating point registers")
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throw java.lang.IllegalArgumentException("$opcode: integer point instruction can't use floating point registers")
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}
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}
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}
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}
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@ -363,10 +358,6 @@ data class Instruction(
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result.add("fr$it")
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result.add("fr$it")
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result.add(",")
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result.add(",")
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}
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}
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fpReg3?.let {
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result.add("fr$it")
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result.add(",")
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}
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value?.let {
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value?.let {
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result.add(it.toString())
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result.add(it.toString())
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result.add(",")
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result.add(",")
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@ -386,7 +377,7 @@ data class Instruction(
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data class InstructionFormat(val datatype: VmDataType?,
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data class InstructionFormat(val datatype: VmDataType?,
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val reg1: Boolean, val reg2: Boolean, val reg3: Boolean,
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val reg1: Boolean, val reg2: Boolean, val reg3: Boolean,
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val fpReg1: Boolean, val fpReg2: Boolean, val fpReg3: Boolean,
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val fpReg1: Boolean, val fpReg2: Boolean,
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val value: Boolean,
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val value: Boolean,
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val fpValue: Boolean) {
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val fpValue: Boolean) {
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companion object {
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companion object {
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@ -398,7 +389,6 @@ data class InstructionFormat(val datatype: VmDataType?,
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var reg3 = false
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var reg3 = false
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var fpreg1 = false
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var fpreg1 = false
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var fpreg2 = false
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var fpreg2 = false
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var fpreg3 = false
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var value = false
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var value = false
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var fpvalue = false
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var fpvalue = false
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val splits = part.splitToSequence(',').iterator()
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val splits = part.splitToSequence(',').iterator()
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@ -410,20 +400,19 @@ data class InstructionFormat(val datatype: VmDataType?,
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"r3" -> reg3=true
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"r3" -> reg3=true
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"fr1" -> fpreg1=true
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"fr1" -> fpreg1=true
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"fr2" -> fpreg2=true
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"fr2" -> fpreg2=true
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"fr3" -> fpreg3=true
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"v" -> value = true
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"v" -> value = true
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"fv" -> fpvalue = true
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"fv" -> fpvalue = true
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else -> throw IllegalArgumentException(spec)
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else -> throw IllegalArgumentException(spec)
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}
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}
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}
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}
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if(typespec=="N")
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if(typespec=="N")
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result[null] = InstructionFormat(null, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, fpReg3=fpreg3, value=value, fpValue=fpvalue)
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result[null] = InstructionFormat(null, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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if('B' in typespec)
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if('B' in typespec)
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result[VmDataType.BYTE] = InstructionFormat(VmDataType.BYTE, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, fpReg3=fpreg3, value=value, fpValue=fpvalue)
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result[VmDataType.BYTE] = InstructionFormat(VmDataType.BYTE, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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if('W' in typespec)
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if('W' in typespec)
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result[VmDataType.WORD] = InstructionFormat(VmDataType.WORD, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, fpReg3=fpreg3, value=value, fpValue=fpvalue)
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result[VmDataType.WORD] = InstructionFormat(VmDataType.WORD, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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if('F' in typespec)
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if('F' in typespec)
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result[VmDataType.FLOAT] = InstructionFormat(VmDataType.FLOAT, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, fpReg3=fpreg3, value=value, fpValue=fpvalue)
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result[VmDataType.FLOAT] = InstructionFormat(VmDataType.FLOAT, reg1=reg1, reg2=reg2, reg3=reg3, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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}
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}
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return result
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return result
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}
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}
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@ -482,10 +471,10 @@ val instructionFormats = mutableMapOf(
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Opcode.DEC to InstructionFormat.from("BW,r1"),
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Opcode.DEC to InstructionFormat.from("BW,r1"),
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Opcode.DECM to InstructionFormat.from("BW,v"),
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Opcode.DECM to InstructionFormat.from("BW,v"),
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Opcode.NEG to InstructionFormat.from("BW,r1 | F,fr1"),
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Opcode.NEG to InstructionFormat.from("BW,r1 | F,fr1"),
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Opcode.ADD to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2,fr3"),
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Opcode.ADD to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2"),
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Opcode.SUB to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2,fr3"),
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Opcode.SUB to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2"),
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Opcode.MUL to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2,fr3"),
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Opcode.MUL to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2"),
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Opcode.DIV to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2,fr3"),
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Opcode.DIV to InstructionFormat.from("BW,r1,r2,r3 | F,fr1,fr2"),
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Opcode.SQRT to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
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Opcode.SQRT to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
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Opcode.SGN to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
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Opcode.SGN to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
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Opcode.RND to InstructionFormat.from("BW,r1 | F,fr1"),
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Opcode.RND to InstructionFormat.from("BW,r1 | F,fr1"),
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@ -515,7 +504,7 @@ val instructionFormats = mutableMapOf(
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Opcode.FTOSB to InstructionFormat.from("F,r1,fr1"),
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Opcode.FTOSB to InstructionFormat.from("F,r1,fr1"),
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Opcode.FTOUW to InstructionFormat.from("F,r1,fr1"),
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Opcode.FTOUW to InstructionFormat.from("F,r1,fr1"),
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Opcode.FTOSW to InstructionFormat.from("F,r1,fr1"),
|
Opcode.FTOSW to InstructionFormat.from("F,r1,fr1"),
|
||||||
Opcode.FPOW to InstructionFormat.from("F,fr1,fr2,fr3"),
|
Opcode.FPOW to InstructionFormat.from("F,fr1,fr2"),
|
||||||
Opcode.FABS to InstructionFormat.from("F,fr1,fr2"),
|
Opcode.FABS to InstructionFormat.from("F,fr1,fr2"),
|
||||||
Opcode.FSIN to InstructionFormat.from("F,fr1,fr2"),
|
Opcode.FSIN to InstructionFormat.from("F,fr1,fr2"),
|
||||||
Opcode.FCOS to InstructionFormat.from("F,fr1,fr2"),
|
Opcode.FCOS to InstructionFormat.from("F,fr1,fr2"),
|
||||||
|
@ -647,7 +647,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
when(i.type!!) {
|
when(i.type!!) {
|
||||||
VmDataType.BYTE -> arithByte("+", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.BYTE -> arithByte("+", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.WORD -> arithWord("+", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.WORD -> arithWord("+", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.FLOAT -> arithFloat("+", i.fpReg1!!, i.fpReg2!!, i.fpReg3!!)
|
VmDataType.FLOAT -> arithFloat("+", i.fpReg1!!, i.fpReg2!!)
|
||||||
}
|
}
|
||||||
pc++
|
pc++
|
||||||
}
|
}
|
||||||
@ -656,7 +656,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
when(i.type!!) {
|
when(i.type!!) {
|
||||||
VmDataType.BYTE -> arithByte("-", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.BYTE -> arithByte("-", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.WORD -> arithWord("-", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.WORD -> arithWord("-", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.FLOAT -> arithFloat("-", i.fpReg1!!, i.fpReg2!!, i.fpReg3!!)
|
VmDataType.FLOAT -> arithFloat("-", i.fpReg1!!, i.fpReg2!!)
|
||||||
}
|
}
|
||||||
pc++
|
pc++
|
||||||
}
|
}
|
||||||
@ -664,7 +664,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
when(i.type!!) {
|
when(i.type!!) {
|
||||||
VmDataType.BYTE -> arithByte("*", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.BYTE -> arithByte("*", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.WORD -> arithWord("*", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.WORD -> arithWord("*", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.FLOAT -> arithFloat("*", i.fpReg1!!, i.fpReg2!!, i.fpReg3!!)
|
VmDataType.FLOAT -> arithFloat("*", i.fpReg1!!, i.fpReg2!!)
|
||||||
}
|
}
|
||||||
pc++
|
pc++
|
||||||
}
|
}
|
||||||
@ -673,7 +673,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
when(i.type!!) {
|
when(i.type!!) {
|
||||||
VmDataType.BYTE -> arithByte("/", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.BYTE -> arithByte("/", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.WORD -> arithWord("/", i.reg1!!, i.reg2!!, i.reg3!!)
|
VmDataType.WORD -> arithWord("/", i.reg1!!, i.reg2!!, i.reg3!!)
|
||||||
VmDataType.FLOAT -> arithFloat("/", i.fpReg1!!, i.fpReg2!!, i.fpReg3!!)
|
VmDataType.FLOAT -> arithFloat("/", i.fpReg1!!, i.fpReg2!!)
|
||||||
}
|
}
|
||||||
pc++
|
pc++
|
||||||
}
|
}
|
||||||
@ -784,9 +784,9 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
registers.setUW(reg1, result.toUShort())
|
registers.setUW(reg1, result.toUShort())
|
||||||
}
|
}
|
||||||
|
|
||||||
private fun arithFloat(operator: String, fpReg1: Int, fpReg2: Int, fpReg3: Int) {
|
private fun arithFloat(operator: String, fpReg1: Int, fpReg2: Int) {
|
||||||
val left = registers.getFloat(fpReg2)
|
val left = registers.getFloat(fpReg1)
|
||||||
val right = registers.getFloat(fpReg3)
|
val right = registers.getFloat(fpReg2)
|
||||||
val result = when(operator) {
|
val result = when(operator) {
|
||||||
"+" -> left + right
|
"+" -> left + right
|
||||||
"-" -> left - right
|
"-" -> left - right
|
||||||
@ -1070,9 +1070,9 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
private fun InsFPOW(i: Instruction) {
|
private fun InsFPOW(i: Instruction) {
|
||||||
val value = registers.getFloat(i.fpReg2!!)
|
val value = registers.getFloat(i.fpReg1!!)
|
||||||
val exponent = registers.getFloat(i.fpReg3!!)
|
val exponent = registers.getFloat(i.fpReg2!!)
|
||||||
registers.setFloat(i.fpReg1!!, value.pow(exponent))
|
registers.setFloat(i.fpReg1, value.pow(exponent))
|
||||||
pc++
|
pc++
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user