mirror of
https://github.com/irmen/prog8.git
synced 2025-01-23 00:31:14 +00:00
support assigning multiple return flags from asmsub in 6502 codegen
This commit is contained in:
Irmen de Jong
parent
64e66e732f
commit
4e98fb75d6
@ -48,6 +48,26 @@ internal class AssignmentAsmGen(
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asmgen.translate(values)
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val assignmentTargets = assignment.children.dropLast(1)
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if(sub.returns.size==assignmentTargets.size) {
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// because we can only handle integer results right now we can just zip() it all up
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val (statusFlagResults, registersResults) = sub.returns.zip(assignmentTargets).partition { it.first.register.statusflag!=null }
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if (statusFlagResults.isEmpty())
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assignRegisterResults(registersResults)
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else if(registersResults.isEmpty())
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assignOnlyTheStatusFlagsResults(false, statusFlagResults)
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else
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assignStatusFlagsAndRegistersResults(statusFlagResults, registersResults)
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} else {
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throw AssemblyError("number of values and targets don't match")
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}
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}
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private fun assignStatusFlagsAndRegistersResults(
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statusFlagResults: List<Pair<StRomSubParameter, PtNode>>,
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registersResults: List<Pair<StRomSubParameter, PtNode>>
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) {
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fun needsToSaveA(registersResults: List<Pair<StRomSubParameter, PtNode>>): Boolean =
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if(registersResults.isEmpty())
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false
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@ -56,124 +76,123 @@ internal class AssignmentAsmGen(
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else
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true
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fun assignCarryFlagResult(target: PtAssignTarget, saveA: Boolean) {
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if(saveA) asmgen.out(" pha")
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asmgen.out(" lda #0 | rol a")
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveA) asmgen.out(" pla")
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if(registersResults.all {
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val tgt = it.second as PtAssignTarget
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tgt.void || tgt.identifier!=null})
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{
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// all other results are just stored into identifiers directly so first handle those
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// (simple store instructions that don't modify the carry flag)
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assignRegisterResults(registersResults)
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assignOnlyTheStatusFlagsResults(false, statusFlagResults)
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} else {
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val saveA = needsToSaveA(registersResults)
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assignOnlyTheStatusFlagsResults(saveA, statusFlagResults)
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assignRegisterResults(registersResults)
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}
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}
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private fun assignOnlyTheStatusFlagsResults(saveA: Boolean, statusFlagResults: List<Pair<StRomSubParameter, PtNode>>) {
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// assigning flags to their variables targets requires load-instructions that destroy flags
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// so if there's more than 1, we need to save and restore the flags
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val saveFlags = statusFlagResults.size>1
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fun hasFlag(statusFlagResults: List<Pair<StRomSubParameter, PtNode>>, flag: Statusflag): PtAssignTarget? {
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for ((returns, target) in statusFlagResults) {
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if(returns.register.statusflag!! == flag)
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return target as PtAssignTarget
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}
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return null
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}
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fun assignZeroFlagResult(target: PtAssignTarget, saveA: Boolean) {
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if(saveA) asmgen.out(" pha")
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asmgen.out("""
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val targetCarry = hasFlag(statusFlagResults, Statusflag.Pc)
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val targetZero = hasFlag(statusFlagResults, Statusflag.Pz)
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val targetNeg = hasFlag(statusFlagResults, Statusflag.Pn)
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val targetOverflow = hasFlag(statusFlagResults, Statusflag.Pv)
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if(saveA) asmgen.out(" pha")
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if(targetZero!=null && !targetZero.void)
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assignZeroFlagResult(targetZero, saveFlags)
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if(targetNeg!=null && !targetNeg.void)
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assignNegativeFlagResult(targetNeg, saveFlags)
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if(targetCarry!=null && !targetCarry.void)
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assignCarryFlagResult(targetCarry)
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if(targetOverflow!=null && !targetOverflow.void)
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assignOverflowFlagResult(targetOverflow)
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if(saveA) asmgen.out(" pla")
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}
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private fun assignRegisterResults(registersResults: List<Pair<StRomSubParameter, PtNode>>) {
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registersResults.forEach { (returns, target) ->
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target as PtAssignTarget
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if(!target.void) {
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val targetIdent = target.identifier
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val targetMem = target.memory
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if(targetIdent!=null || targetMem!=null) {
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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when(returns.type) {
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in ByteDatatypesWithBoolean -> {
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if(returns.register.registerOrPair in Cx16VirtualRegisters) {
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assignVirtualRegister(tgt, returns.register.registerOrPair!!)
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} else {
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assignRegisterByte(tgt, returns.register.registerOrPair!!.asCpuRegister(), false, false)
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}
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}
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in WordDatatypes -> {
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assignRegisterpairWord(tgt, returns.register.registerOrPair!!)
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}
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else -> throw AssemblyError("weird dt")
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}
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}
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else TODO("array target for multi-value assignment") // Not done yet due to result register clobbering complexity
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}
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}
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}
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private fun assignCarryFlagResult(target: PtAssignTarget) {
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// overflow is not clobbered so no need to save/restore it
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asmgen.out(" lda #0 | rol a")
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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}
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private fun assignZeroFlagResult(target: PtAssignTarget, saveFlags: Boolean) {
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if(saveFlags) asmgen.out(" php")
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asmgen.out("""
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beq +
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lda #0
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beq ++
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+ lda #1
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+""")
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveA) asmgen.out(" pla")
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}
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveFlags) asmgen.out(" plp")
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}
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fun assignNegativeFlagResult(target: PtAssignTarget, saveA: Boolean) {
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if(saveA) asmgen.out(" pha")
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asmgen.out("""
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private fun assignNegativeFlagResult(target: PtAssignTarget, saveFlags: Boolean) {
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if(saveFlags) asmgen.out(" php")
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asmgen.out("""
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bmi +
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lda #0
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beq ++
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+ lda #1
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+""")
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveA) asmgen.out(" pla")
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}
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveFlags) asmgen.out(" plp")
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}
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fun assignOverflowFlagResult(target: PtAssignTarget, saveA: Boolean) {
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if(saveA) asmgen.out(" pha")
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asmgen.out("""
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private fun assignOverflowFlagResult(target: PtAssignTarget) {
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// overflow is not clobbered so no need to save/restore it
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asmgen.out("""
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bvs +
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lda #0
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beq ++
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+ lda #1
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+""")
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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if(saveA) asmgen.out(" pla")
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}
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fun assignRegisterResults(registersResults: List<Pair<StRomSubParameter, PtNode>>) {
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registersResults.forEach { (returns, target) ->
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target as PtAssignTarget
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if(!target.void) {
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val targetIdent = target.identifier
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val targetMem = target.memory
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if(targetIdent!=null || targetMem!=null) {
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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when(returns.type) {
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in ByteDatatypesWithBoolean -> {
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if(returns.register.registerOrPair in Cx16VirtualRegisters) {
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assignVirtualRegister(tgt, returns.register.registerOrPair!!)
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} else {
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assignRegisterByte(tgt, returns.register.registerOrPair!!.asCpuRegister(), false, false)
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}
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}
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in WordDatatypes -> {
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assignRegisterpairWord(tgt, returns.register.registerOrPair!!)
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}
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else -> throw AssemblyError("weird dt")
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}
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}
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else TODO("array target for multi-value assignment") // Not done yet due to result register clobbering complexity
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}
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}
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}
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val assignmentTargets = assignment.children.dropLast(1)
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if(sub.returns.size==assignmentTargets.size) {
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// because we can only handle integer results right now we can just zip() it all up
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val (statusFlagResults, registersResults) = sub.returns.zip(assignmentTargets).partition { it.first.register.statusflag!=null }
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if(statusFlagResults.isNotEmpty()) {
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if(statusFlagResults.size>1)
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TODO("handle multiple status flag results")
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val (returns, target) = statusFlagResults.single()
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target as PtAssignTarget
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if(target.void) {
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// forget about the Carry status flag, only assign the normal return values
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assignRegisterResults(registersResults)
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return
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}
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if(registersResults.all {
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val tgt = it.second as PtAssignTarget
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tgt.void || tgt.identifier!=null})
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{
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// all other results are just stored into identifiers directly so first handle those
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// (simple store instructions that don't modify the carry flag)
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assignRegisterResults(registersResults)
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return when(returns.register.statusflag!!) {
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Statusflag.Pc -> assignCarryFlagResult(target, false)
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Statusflag.Pz -> assignZeroFlagResult(target, false)
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Statusflag.Pv -> assignOverflowFlagResult(target, false)
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Statusflag.Pn -> assignNegativeFlagResult(target, false)
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}
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}
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val saveA = needsToSaveA(registersResults)
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when(returns.register.statusflag!!) {
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Statusflag.Pc -> assignCarryFlagResult(target, saveA)
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Statusflag.Pz -> assignZeroFlagResult(target, saveA)
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Statusflag.Pv -> assignOverflowFlagResult(target, saveA)
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Statusflag.Pn -> assignNegativeFlagResult(target, saveA)
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}
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}
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assignRegisterResults(registersResults)
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} else {
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throw AssemblyError("number of values and targets don't match")
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}
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val tgt = AsmAssignTarget.fromAstAssignment(target, target.definingISub(), asmgen)
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assignRegisterByte(tgt, CpuRegister.A, false, false)
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}
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fun translateNormalAssignment(assign: AsmAssignment, scope: IPtSubroutine?) {
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when(assign.source.kind) {
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SourceStorageKind.LITERALBOOLEAN -> {
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@ -57,10 +57,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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RegisterOrPair.XY -> IRInstruction(Opcode.LOADHXY, IRDataType.WORD, reg1=regNum)
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in Cx16VirtualRegisters -> IRInstruction(Opcode.LOADM, IRDataType.WORD, reg1=regNum, labelSymbol = "cx16.${returns.register.registerOrPair.toString().lowercase()}")
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null -> {
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when(returns.register.statusflag) {
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Statusflag.Pc -> IRInstruction(Opcode.LOADHA, IRDataType.BYTE, reg1=regNum)
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else -> throw AssemblyError("weird statusflag as returnvalue")
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}
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TODO("assign CPU status flag ${returns.register.statusflag!!}")
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}
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else -> throw AssemblyError("cannot load register")
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}
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@ -10,8 +10,8 @@ import prog8.code.ast.PtAssignTarget
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import prog8.code.ast.PtAssignment
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import prog8.code.core.DataType
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import prog8.code.core.SourceCode
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import prog8.code.target.C64Target
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import prog8.code.target.Cx16Target
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import prog8.code.target.VMTarget
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import prog8.parser.Prog8Parser.parseModule
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import prog8tests.helpers.ErrorReporterForTests
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import prog8tests.helpers.compileText
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@ -136,7 +136,7 @@ main {
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}}
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}
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}"""
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compileText(VMTarget(), false, src, writeAssembly = true) shouldNotBe null
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compileText(C64Target(), false, src, writeAssembly = true) shouldNotBe null
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val errors = ErrorReporterForTests()
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val result = compileText(Cx16Target(), false, src, errors, true)!!
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errors.errors.size shouldBe 0
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@ -186,7 +186,7 @@ main {
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romsub ${'$'}8003 = test3() -> uword @R1, bool @Pc, ubyte @X
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}"""
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compileText(VMTarget(), false, src, writeAssembly = true) shouldNotBe null
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compileText(C64Target(), false, src, writeAssembly = true) shouldNotBe null
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val errors = ErrorReporterForTests()
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val result = compileText(Cx16Target(), false, src, errors, true)!!
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errors.errors.size shouldBe 0
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@ -420,4 +420,24 @@ main {
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compileText(Cx16Target(), true, src, writeAssembly = true) shouldNotBe null
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compileText(Cx16Target(), false, src, writeAssembly = true) shouldNotBe null
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}
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test("multiple status flags return values from asmsub") {
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val src="""
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main {
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romsub 5000 = carryAndNegativeAndByteAndWord() -> bool @Pc, bool @Pn, ubyte @X, uword @AY
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sub start() {
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ubyte @shared x
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uword @shared w
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bool @shared flag1
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bool @shared flag2
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flag1, flag2, x, w = carryAndNegativeAndByteAndWord()
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flag1, void, void, w = carryAndNegativeAndByteAndWord()
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void, void, void, void = carryAndNegativeAndByteAndWord()
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void carryAndNegativeAndByteAndWord()
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}
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}"""
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compileText(Cx16Target(), false, src, writeAssembly = true) shouldNotBe null
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}
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})
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139
examples/test.p8
139
examples/test.p8
@ -2,15 +2,142 @@
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%zeropage basicsafe
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%option no_sysinit
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main {
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sub start() {
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byte @shared x
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word @shared w
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ubyte @shared x
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uword @shared w
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bool flag1, flag2
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if x==0 or x==1 or x==2
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x++
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sys.clear_carry()
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flag1 = onlyCarry()
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if flag1
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txt.print("1: ok\n")
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else
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txt.print("1: fail\n")
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if w==0 or w==1 or w==2
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x++
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x=1
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flag1 = onlyZero()
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if flag1
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txt.print("2: ok\n")
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else
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txt.print("2: fail\n")
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sys.clear_carry()
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flag1, x = carryAndByte()
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if flag1 and x==42
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txt.print("3: ok\n")
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else
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txt.print("3: fail\n")
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sys.clear_carry()
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flag1, w = carryAndWord()
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if flag1 and w==4242
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txt.print("4: ok\n")
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else
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txt.print("4: fail\n")
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sys.clear_carry()
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flag1, x, w = carryAndValues()
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if flag1 and x==99 and w==9999
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txt.print("5: ok\n")
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else
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txt.print("5: fail\n")
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x = 1
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sys.clear_carry()
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flag1, flag2 = onlyCarryAndZero()
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if flag1 and flag2
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txt.print("6: ok\n")
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else
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txt.print("6: fail\n")
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x = 1
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sys.clear_carry()
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flag1, flag2, x = carryAndZeroAndByte()
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if flag1 and flag2 and x==33
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txt.print("7: ok\n")
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else
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txt.print("7: fail\n")
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x = 1
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sys.clear_carry()
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flag1, flag2, x, w = carryAndNegativeAndByteAndWord()
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if flag1 and flag2 and x==55 and w==51400
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txt.print("8: ok\n")
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else
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txt.print("8: fail\n")
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}
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asmsub carryAndNegativeAndByteAndWord() -> bool @Pc, bool @Pn, ubyte @X, uword @AY {
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%asm {{
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ldx #55
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lda #200
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ldy #200
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sec
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rts
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}}
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}
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asmsub carryAndZeroAndByte() -> bool @Pc, bool @Pz, ubyte @Y {
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%asm {{
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ldy #33
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lda #0
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sec
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rts
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}}
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}
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asmsub onlyCarryAndZero() -> bool @Pc, bool @Pz {
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%asm {{
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lda #0
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sec
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rts
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}}
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}
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asmsub carryAndValues() -> bool @Pc, ubyte @X, uword @AY {
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%asm {{
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ldx #99
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lda #<9999
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ldy #>9999
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sec
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rts
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}}
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}
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asmsub carryAndWord() -> bool @Pc, uword @AY {
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%asm {{
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lda #<4242
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ldy #>4242
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sec
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rts
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}}
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}
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asmsub carryAndByte() -> bool @Pc, ubyte @A {
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%asm {{
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lda #42
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sec
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rts
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}}
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}
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asmsub onlyCarry() -> bool @Pc {
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%asm {{
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sec
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rts
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}}
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}
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asmsub onlyZero() -> bool @Pz {
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%asm {{
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lda #0
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rts
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}}
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}
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}
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