fix compiler crash when extsub has both FAC1 and FAC2 float parameters

codeGenCpu6502/src/prog8/codegen/cpu6502/AsmsubHelpers.kt

@@ -11,18 +11,22 @@ fun asmsub6502ArgsEvalOrder(sub: PtAsmSub): List<Int> {
     //  1) cx16 virtual word registers,
     //  2) paired CPU registers,
     //  3) single CPU registers (order Y,X,A),
-    //  4) CPU Carry status flag
+    //  4) floating point registers (FAC1, FAC2),
+    //  5) CPU Carry status flag
     val args = sub.parameters.withIndex()
     val (cx16regs, args2) = args.partition { it.value.first.registerOrPair in Cx16VirtualRegisters }
     val pairedRegisters = arrayOf(RegisterOrPair.AX, RegisterOrPair.AY, RegisterOrPair.XY)
     val (pairedRegs , args3) = args2.partition { it.value.first.registerOrPair in pairedRegisters }
-    val (singleRegs, rest) = args3.partition { it.value.first.registerOrPair != null }
+    val (singleRegsMixed, rest) = args3.partition { it.value.first.registerOrPair != null }
+    val (singleCpuRegs, floatRegs) = singleRegsMixed.partition {it.value.first.registerOrPair != RegisterOrPair.FAC1 && it.value.first.registerOrPair != RegisterOrPair.FAC2  }
 
     cx16regs.forEach { order += it.index }
     pairedRegs.forEach { order += it.index }
-    singleRegs.sortedBy { it.value.first.registerOrPair!!.asCpuRegister() }.asReversed().forEach { order += it.index }
+    singleCpuRegs.sortedBy { it.value.first.registerOrPair!!.asCpuRegister() }.asReversed().forEach { order += it.index }
     require(rest.all { it.value.first.registerOrPair==null && it.value.first.statusflag!=null})
+    floatRegs.forEach { order += it.index }
     rest.forEach { order += it.index }
     require(order.size==sub.parameters.size)
+
     return order
 }

codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt

@@ -608,6 +608,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                         RegisterOrPair.AX -> addInstr(result, IRInstruction(Opcode.STOREHAX, IRDataType.WORD, reg1=tr.resultReg), null)
                         RegisterOrPair.AY -> addInstr(result, IRInstruction(Opcode.STOREHAY, IRDataType.WORD, reg1=tr.resultReg), null)
                         RegisterOrPair.XY -> addInstr(result, IRInstruction(Opcode.STOREHXY, IRDataType.WORD, reg1=tr.resultReg), null)
+                        RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> TODO("floating point register parameters not supported")
                         in Cx16VirtualRegisters -> {
                             addInstr(result, IRInstruction(Opcode.STOREM, paramDt, reg1=tr.resultReg, labelSymbol = "cx16.${parameter.register.registerOrPair.toString().lowercase()}"), null)
                         }

docs/source/todo.rst

@@ -1,7 +1,7 @@
 TODO
 ====
 
-support this usage of defer:
+support this usage of defer somehow?:
 
         if diskio.f_open(filename) {
             defer diskio.f_close()
@@ -51,6 +51,7 @@ Future Things and Ideas
 
 - ir: support %align on code chunks
 - ir: fix call() return value handling
+- ir: fix float register parameters (FAC1,FAC2) for extsubs, search for TODO("floating point register parameters not supported")
 - ir: proper code gen for the CALLI instruction and that it (optionally) returns a word value that needs to be assigned to a reg
 - ir: idea: (but LLVM IR simply keeps the variables, so not a good idea then?...): replace all scalar variables by an allocated register. Keep a table of the variable to register mapping (including the datatype)
   global initialization values are simply a list of LOAD instructions.

examples/test.p8

@@ -1,13 +1,13 @@
-%import textio
+%import floats
 %option no_sysinit
 %zeropage basicsafe
 
 main {
+
+    extsub $8000 = routine(float xx @FAC1, float yy @FAC2)
+
     sub start() {
-        cx16.r0=0
-        repeat 65536 {
-            cx16.r0++
-        }
-        txt.print_uw(cx16.r0)
+        @($8000) = $60
+        routine(1.234, 2.3445)
     }
 }