From 5190594c8a03bf951533319fafd0c602090635dc Mon Sep 17 00:00:00 2001
From: Irmen de Jong <irmen@razorvine.net>
Date: Sun, 14 Nov 2021 12:23:46 +0100
Subject: [PATCH] added several more assembly-level optimizations to remove
 redundant instructions

---
 .../target/cpu6502/codegen/AsmOptimizer.kt    | 114 ++++++++++++++++++
 .../compiler/BeforeAsmGenerationAstChanger.kt |   4 +
 docs/source/todo.rst                          |   1 +
 3 files changed, 119 insertions(+)

diff --git a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmOptimizer.kt b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmOptimizer.kt
index aad750514..cb8f152b8 100644
--- a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmOptimizer.kt
+++ b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmOptimizer.kt
@@ -174,7 +174,121 @@ private fun optimizeSameAssignments(linesByFourteen: List<List<IndexedValue<Stri
                 }
             }
         }
+
+        var overlappingMods = false
+        /*
+        sta  prog8_lib.retval_intermX      ; remove
+        sty  prog8_lib.retval_intermY      ; remove
+        lda  prog8_lib.retval_intermX      ; remove
+        ldy  prog8_lib.retval_intermY      ; remove
+        sta  A1
+        sty  A2
+         */
+        if(first.startsWith("st") && second.startsWith("st")
+            && third.startsWith("ld") && fourth.startsWith("ld")
+            && fifth.startsWith("st") && sixth.startsWith("st")) {
+            val reg1 = first[2]
+            val reg2 = second[2]
+            val reg3 = third[2]
+            val reg4 = fourth[2]
+            val reg5 = fifth[2]
+            val reg6 = sixth[2]
+            if (reg1 == reg3 && reg1 == reg5 && reg2 == reg4 && reg2 == reg6) {
+                val firstvalue = first.substring(4)
+                val secondvalue = second.substring(4)
+                val thirdvalue = third.substring(4)
+                val fourthvalue = fourth.substring(4)
+                if(firstvalue.contains("prog8_lib.retval_interm") && secondvalue.contains("prog8_lib.retval_interm")
+                    && firstvalue==thirdvalue && secondvalue==fourthvalue) {
+                    mods.add(Modification(lines[0].index, true, null))
+                    mods.add(Modification(lines[1].index, true, null))
+                    mods.add(Modification(lines[2].index, true, null))
+                    mods.add(Modification(lines[3].index, true, null))
+                    overlappingMods = true
+                }
+            }
+        }
+
+        /*
+        sta  A1
+        sty  A2
+        lda  A1     ; can be removed
+        ldy  A2     ; can be removed if not followed by a branch instuction
+         */
+        if(!overlappingMods && first.startsWith("st") && second.startsWith("st")
+            && third.startsWith("ld") && fourth.startsWith("ld")) {
+            val reg1 = first[2]
+            val reg2 = second[2]
+            val reg3 = third[2]
+            val reg4 = fourth[2]
+            if(reg1==reg3 && reg2==reg4) {
+                val firstvalue = first.substring(4)
+                val secondvalue = second.substring(4)
+                val thirdvalue = third.substring(4)
+                val fourthvalue = fourth.substring(4)
+                if(firstvalue==thirdvalue && secondvalue == fourthvalue) {
+                    overlappingMods = true
+                    mods.add(Modification(lines[2].index, true, null))
+                    if(!fifth.startsWith('b'))
+                        mods.add(Modification(lines[3].index, true, null))
+                }
+            }
+        }
+        /*
+        sta  A1
+        sty  A2
+        lda  A1     ; can be removed if not followed by a branch instruction
+         */
+        if(!overlappingMods && first.startsWith("st") && second.startsWith("st")
+            && third.startsWith("ld") && !fourth.startsWith("b")) {
+            val reg1 = first[2]
+            val reg3 = third[2]
+            if(reg1==reg3) {
+                val firstvalue = first.substring(4)
+                val thirdvalue = third.substring(4)
+                if(firstvalue==thirdvalue) {
+                    overlappingMods = true
+                    mods.add(Modification(lines[2].index, true, null))
+                }
+            }
+        }
+        /*
+        sta  A1
+        <other st/ld instruction not involving A1>
+        sta  A1     ; can be removed
+         */
+        if(!overlappingMods && first.startsWith("st") && third.startsWith("st")) {
+            val reg1 = first[2]
+            val reg3 = third[2]
+            if(reg1==reg3 && (second.startsWith("ld") || second.startsWith("st"))) {
+                val firstvalue = first.substring(4)
+                val secondvalue = second.substring(4)
+                val thirdvalue = third.substring(4)
+                if(firstvalue==thirdvalue && firstvalue!=secondvalue) {
+                    overlappingMods = true
+                    mods.add(Modification(lines[2].index, true, null))
+                }
+            }
+        }
+        /*
+        sta  A1
+        ldy  A1     ; make tay
+        sta  A1     ; remove
+         */
+        if(!overlappingMods && first.startsWith("sta") && second.startsWith("ld")
+            && third.startsWith("sta") && second.length>4) {
+            val firstvalue = first.substring(4)
+            val secondvalue = second.substring(4)
+            val thirdvalue = third.substring(4)
+            if(firstvalue==secondvalue && firstvalue==thirdvalue) {
+                overlappingMods = true
+                val reg2 = second[2]
+                mods.add(Modification(lines[1].index, false, "  ta$reg2"))
+                mods.add(Modification(lines[2].index, true, null))
+            }
+        }
     }
+
     return mods
 }
 
diff --git a/compiler/src/prog8/compiler/BeforeAsmGenerationAstChanger.kt b/compiler/src/prog8/compiler/BeforeAsmGenerationAstChanger.kt
index b853614df..cebb6a8d8 100644
--- a/compiler/src/prog8/compiler/BeforeAsmGenerationAstChanger.kt
+++ b/compiler/src/prog8/compiler/BeforeAsmGenerationAstChanger.kt
@@ -239,6 +239,10 @@ internal class BeforeAsmGenerationAstChanger(val program: Program, private val o
         var leftOperandReplacement: Expression? = null
         var rightAssignment: Assignment? = null
         var rightOperandReplacement: Expression? = null
+
+
+        // TODO don't optimize simple conditionals that are just a function call
+
         if(!expr.left.isSimple) {
             val dt = expr.left.inferType(program)
             val name = when {
diff --git a/docs/source/todo.rst b/docs/source/todo.rst
index f86e92e5d..6d3c9e15c 100644
--- a/docs/source/todo.rst
+++ b/docs/source/todo.rst
@@ -3,6 +3,7 @@ TODO
 
 For next compiler release (7.3)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+- simplifyConditionalExpression: don't change conditinal expressions that are just a single function call
 - add expression simplification to while and until loops as well.