Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2024-06-10 20:29:33 +00:00
Code Issues Projects Releases Wiki Activity

consolidate word comparison codegen

Browse Source
This commit is contained in:
Irmen de Jong 2024-03-01 22:43:31 +01:00
parent 047decd552
commit 58d9463f16
4 changed files with 33 additions and 299 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AnyExprAsmGen.kt
View File

@ -23,7 +23,7 @@ internal class AnyExprAsmGen(
return assignByteBinExpr(expr, assign)
if (expr.left.type in WordDatatypes && expr.right.type in WordDatatypes) {
require(expr.operator in ComparisonOperators)
throw AssemblyError("words operands comparison -> byte, should have been handled by assignOptimizedComparisonWords()")
throw AssemblyError("words operands comparison -> byte, should have been handled elsewhere")
}
if (expr.left.type==DataType.FLOAT && expr.right.type==DataType.FLOAT) {
require(expr.operator in ComparisonOperators)

296
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AssignmentAsmGen.kt
View File

@ -429,11 +429,6 @@ internal class AssignmentAsmGen(private val program: PtProgram,
}
}
if(expr.left.type in WordDatatypes && expr.right.type in WordDatatypes) {
if(assignOptimizedComparisonWords(expr, assign)) // TODO remove this!
return true
}
// b = v > 99 --> b=false , if v>99 b=true
val targetReg=assign.target.register
if(targetReg!=null) {
@ -1206,297 +1201,6 @@ internal class AssignmentAsmGen(private val program: PtProgram,
return false
}
private fun assignOptimizedComparisonWords(expr: PtBinaryExpression, assign: AsmAssignment): Boolean {
val signed = expr.left.type == DataType.WORD || expr.right.type == DataType.WORD
when(expr.operator) {
"==" -> {
if(expr.left is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.left as PtIdentifier)
asmgen.assignExpressionToRegister(expr.right, RegisterOrPair.AY)
asmgen.out("""
cmp $varName
bne +
cpy $varName+1
bne +
lda #1
bne ++
+ lda #0
+""")
} else {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
bne +
cpy P8ZP_SCRATCH_W1+1
bne +
lda #1
bne ++
+ lda #0
+""")
}
}
"!=" -> {
if(expr.left is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.left as PtIdentifier)
asmgen.assignExpressionToRegister(expr.right, RegisterOrPair.AY)
asmgen.out("""
cmp $varName
bne +
cpy $varName+1
bne +
lda #0
beq ++
+ lda #1
+""")
} else {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
bne +
cpy P8ZP_SCRATCH_W1+1
bne +
lda #0
beq ++
+ lda #1
+""")
}
}
"<" -> {
if(expr.right is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.right as PtIdentifier)
asmgen.assignExpressionToRegister(expr.left, RegisterOrPair.AY)
if(signed)
asmgen.out("""
cmp $varName
tya
sbc $varName+1
bvc +
eor #${'$'}80
+ bpl ++
+ lda #1
bne ++
+ lda #0
+""")
else
asmgen.out("""
cpy $varName+1
bcc +
bne ++
cmp $varName
bcs ++
+ lda #1
bne ++
+ lda #0
+""")
} else {
if(signed) {
asmgen.assignWordOperandsToAYAndVar(expr.left, expr.right, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
tya
sbc P8ZP_SCRATCH_W1+1
bvc +
eor #${'$'}80
+ bpl ++
+ lda #1
bne ++
+ lda #0
+""")
}
else {
asmgen.assignWordOperandsToAYAndVar(expr.left, expr.right, "P8ZP_SCRATCH_W1")
asmgen.out("""
cpy P8ZP_SCRATCH_W1+1
bcc +
bne ++
cmp P8ZP_SCRATCH_W1
bcs ++
+ lda #1
bne ++
+ lda #0
+""")
}
}
}
"<=" -> {
if(expr.left is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.left as PtIdentifier)
asmgen.assignExpressionToRegister(expr.right, RegisterOrPair.AY)
if(signed)
asmgen.out("""
cmp $varName
tya
sbc $varName+1
bvc +
eor #${'$'}80
+ bmi +
lda #1
bne ++
+ lda #0
+""")
else
asmgen.out("""
cpy $varName+1
bcc ++
bne +
cmp $varName
bcc ++
+ lda #1
bne ++
+ lda #0
+""")
} else {
if(signed) {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
tya
sbc P8ZP_SCRATCH_W1+1
bvc +
eor #${'$'}80
+ bmi +
lda #1
bne ++
+ lda #0
+""")
}
else {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cpy P8ZP_SCRATCH_W1+1
bcc ++
bne +
cmp P8ZP_SCRATCH_W1
bcc ++
+ lda #1
bne ++
+ lda #0
+""")
}
}
}
">" -> {
if(expr.left is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.left as PtIdentifier)
asmgen.assignExpressionToRegister(expr.right, RegisterOrPair.AY)
if(signed)
asmgen.out("""
cmp $varName
tya
sbc $varName+1
bvc +
eor #${'$'}80
+ bpl ++
+ lda #1
bne ++
+ lda #0
+""")
else
asmgen.out("""
cpy $varName+1
bcc +
bne ++
cmp $varName
bcs ++
+ lda #1
bne ++
+ lda #0
+""")
} else {
if(signed) {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
tya
sbc P8ZP_SCRATCH_W1+1
bvc +
eor #${'$'}80
+ bpl ++
+ lda #1
bne ++
+ lda #0
+""")
}
else {
asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "P8ZP_SCRATCH_W1")
asmgen.out("""
cpy P8ZP_SCRATCH_W1+1
bcc +
bne ++
cmp P8ZP_SCRATCH_W1
bcs ++
+ lda #1
bne ++
+ lda #0
+""")
}
}
}
">=" -> {
if(expr.right is PtIdentifier) {
val varName = asmgen.asmVariableName(expr.right as PtIdentifier)
asmgen.assignExpressionToRegister(expr.left, RegisterOrPair.AY)
if(signed)
asmgen.out("""
cmp $varName
tya
sbc $varName+1
bvc +
eor #${'$'}80
+ bmi +
lda #1
bne ++
+ lda #0
+""")
else
asmgen.out("""
cpy $varName+1
bcc ++
bne +
cmp $varName
bcc ++
+ lda #1
bne ++
+ lda #0
+""")
} else {
if(signed) {
asmgen.assignWordOperandsToAYAndVar(expr.left, expr.right, "P8ZP_SCRATCH_W1")
asmgen.out("""
cmp P8ZP_SCRATCH_W1
tya
sbc P8ZP_SCRATCH_W1+1
bvc +
eor #${'$'}80
+ bmi +
lda #1
bne ++
+ lda #0
+""")
}
else {
asmgen.assignWordOperandsToAYAndVar(expr.left, expr.right, "P8ZP_SCRATCH_W1")
asmgen.out("""
cpy P8ZP_SCRATCH_W1+1
bcc ++
bne +
cmp P8ZP_SCRATCH_W1
bcc ++
+ lda #1
bne ++
+ lda #0
+""")
}
}
}
else -> return false
}
assignRegisterByte(assign.target, CpuRegister.A, signed, true)
return true
}
private fun assignBitwiseWithSimpleRightOperandByte(target: AsmAssignTarget, left: PtExpression, operator: String, right: PtExpression) {
assignExpressionToRegister(left, RegisterOrPair.A, false)
val operand = when(right) {

24
docs/source/todo.rst
View File

@ -1,10 +1,30 @@
TODO
====
textelite is larger
add asm optimizer:
LDA NUM1
CMP NUM2
BCC LABEL
BEQ LABEL
(or something similar) which branches to LABEL when NUM1 <= NUM2. (In this case NUM1 and NUM2 are unsigned numbers.) However, consider the following sequence:
LDA NUM2
CMP NUM1
BCS LABEL
larger programs:
automatons
mandelbrot (quite a bit larger)
mandelbrot-gfx
maze
textelite
rockrunner is quite a bit larger
optimize assignOptimizedComparisonWords for when comparing to simple things like number and identifier. (get rid of it completely by just rewriting everything into an if-else statement?)
optimize optimizedPlusMinExpr for when comparing to simple things like number and identifier.
replace Takes by Http4k in httpCompilerService project. https://github.com/http4k/examples/blob/master/hello-world/README.md

10
examples/test.p8
View File

@ -4,6 +4,16 @@
main {
sub start() {
ubyte[] flakes = [1,2,3]
ubyte @shared idx = 2
if flakes[idx]==239 {
txt.print("yes")
} else {
txt.print("nope")
}
ubyte @shared xx = 16
ubyte @shared yy = 20