fix non-existing instructions txy/tyx, oops

This commit is contained in:
Irmen de Jong 2023-12-29 03:27:35 +01:00
parent e35cfd4971
commit 5d88717f32
3 changed files with 2 additions and 9 deletions

View File

@ -381,15 +381,9 @@ private fun optimizeStoreLoadSame(
} else if(first=="phx" && second=="pla") {
mods.add(Modification(lines[1].index, true, null))
mods.add(Modification(lines[2].index, false, " txa"))
} else if(first=="phx" && second=="ply") {
mods.add(Modification(lines[1].index, true, null))
mods.add(Modification(lines[2].index, false, " txy"))
} else if(first=="phy" && second=="pla") {
mods.add(Modification(lines[1].index, true, null))
mods.add(Modification(lines[2].index, false, " tya"))
} else if(first=="phy" && second=="plx") {
mods.add(Modification(lines[1].index, true, null))
mods.add(Modification(lines[2].index, false, " tyx"))
}
}
return mods

View File

@ -3040,7 +3040,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
CpuRegister.X -> when(target.register!!) {
RegisterOrPair.A -> { asmgen.out(" txa") }
RegisterOrPair.X -> { }
RegisterOrPair.Y -> { asmgen.out(" txy") }
RegisterOrPair.Y -> { asmgen.out(" stx P8ZP_SCRATCH_REG | ldy P8ZP_SCRATCH_REG") }
RegisterOrPair.AY -> {
require(extendWord)
if(signed)
@ -3090,7 +3090,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
}
CpuRegister.Y -> when(target.register!!) {
RegisterOrPair.A -> { asmgen.out(" tya") }
RegisterOrPair.X -> { asmgen.out(" tyx") }
RegisterOrPair.X -> { asmgen.out(" sty P8ZP_SCRATCH_REG | ldx P8ZP_SCRATCH_REG") }
RegisterOrPair.Y -> { }
RegisterOrPair.AY -> {
require(extendWord)

View File

@ -2,7 +2,6 @@
TODO
====
- fix "txy" and "tyx" non-existing instructions (assembler/experiment/* causes them to be used)
- fix a1%a2 being parsed as directive
- fix bitshift.p8
- add crc8 and crc16 and crc32 to math