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https://github.com/irmen/prog8.git
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enable more optimizations for typecasted assignments. Fixed missing codegen for assigning bytes to words in certain cases.
This commit is contained in:
Irmen de Jong
parent
fa48746ba9
commit
5ecf2a3357
@ -1584,6 +1584,16 @@ internal class BuiltinFunctionsAsmGen(private val program: Program, private val
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null, RegisterOrPair.A -> asmgen.out(" lda $sourceName+1")
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RegisterOrPair.X -> asmgen.out(" ldx $sourceName+1")
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RegisterOrPair.Y -> asmgen.out(" ldy $sourceName+1")
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName+1 | ldx #0")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName+1 | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName+1 | ldy #0")
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in Cx16VirtualRegisters -> {
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val regname = resultRegister.name.lowercase()
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" lda $sourceName+1 | sta cx16.$regname | stz cx16.$regname+1")
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else
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asmgen.out(" lda $sourceName+1 | sta cx16.$regname | lda #0 | sta cx16.$regname+1")
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}
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else -> throw AssemblyError("invalid reg")
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}
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}
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@ -1629,6 +1639,16 @@ internal class BuiltinFunctionsAsmGen(private val program: Program, private val
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null, RegisterOrPair.A -> asmgen.out(" lda $sourceName")
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RegisterOrPair.X -> asmgen.out(" ldx $sourceName")
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RegisterOrPair.Y -> asmgen.out(" ldy $sourceName")
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName | ldx #0")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy #0")
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in Cx16VirtualRegisters -> {
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val regname = resultRegister.name.lowercase()
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" lda $sourceName | sta cx16.$regname | stz cx16.$regname+1")
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else
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asmgen.out(" lda $sourceName | sta cx16.$regname | lda #0 | sta cx16.$regname+1")
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}
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else -> throw AssemblyError("invalid reg")
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}
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}
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@ -1520,7 +1520,7 @@ $containsLabel lda #1
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pha
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ora #$7f
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bmi +
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ldx #0
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lda #0
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+ tax
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pla""")
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RegisterOrPair.AY -> asmgen.out("""
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@ -1528,7 +1528,7 @@ $containsLabel lda #1
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pha
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ora #$7f
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bmi +
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ldy #0
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lda #0
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+ tay
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pla""")
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RegisterOrPair.XY -> asmgen.out("""
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@ -1536,9 +1536,19 @@ $containsLabel lda #1
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tax
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ora #$7f
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bmi +
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ldy #0
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lda #0
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+ tay""")
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else -> throw AssemblyError("only reg pairs are words")
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in Cx16VirtualRegisters -> {
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val regname = wordtarget.register.name.lowercase()
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asmgen.out("""
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lda $sourceName
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sta cx16.$regname
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ora #$7f
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bmi +
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lda #0
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+ sta cx16.$regname+1""")
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}
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else -> throw AssemblyError("only reg pairs allowed as word target ${wordtarget.register}")
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}
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}
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TargetStorageKind.STACK -> {
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@ -1589,7 +1599,14 @@ $containsLabel lda #1
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda $sourceName")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda $sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx $sourceName")
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else -> throw AssemblyError("only reg pairs are words")
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in Cx16VirtualRegisters -> {
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val regname = wordtarget.register.name.lowercase()
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" lda $sourceName | sta cx16.$regname | stz cx16.$regname+1")
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else
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asmgen.out(" lda $sourceName | sta cx16.$regname | lda #0 | sta cx16.$regname+1")
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}
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else -> throw AssemblyError("only reg pairs allowed as word target")
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}
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}
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TargetStorageKind.STACK -> {
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@ -181,9 +181,8 @@ class TestTypecasts: FunSpec({
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}
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}"""
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val result = compileText(C64Target, false, text, writeAssembly = true).assertSuccess()
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printProgram(result.program)
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val statements = result.program.entrypoint.statements
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statements.size shouldBe 16
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statements.size shouldBe 14
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}
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test("no infinite typecast loop in assignment asmgen") {
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@ -200,4 +199,52 @@ class TestTypecasts: FunSpec({
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"""
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compileText(C64Target, false, text, writeAssembly = true).assertSuccess()
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}
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test("(u)byte extend to word parameters") {
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val text = """
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main {
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sub start() {
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byte ub1 = -50
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byte ub2 = -51
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byte ub3 = -52
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byte ub4 = 100
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word @shared ww = func(ub1, ub2, ub3, ub4)
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ww = func(ub4, ub2, ub3, ub1)
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ww=afunc(ub1, ub2, ub3, ub4)
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ww=afunc(ub4, ub2, ub3, ub1)
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}
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sub func(word x1, word y1, word x2, word y2) -> word {
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return x1
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}
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asmsub afunc(word x1 @R0, word y1 @R1, word x2 @R2, word y2 @R3) -> word @AY {
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%asm {{
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lda cx16.r0
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ldy cx16.r0+1
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rts
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}}
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}
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}"""
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compileText(C64Target, true, text, writeAssembly = true).assertSuccess()
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}
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test("lsb msb used as args with word types") {
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val text = """
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main {
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sub start() {
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uword xx=${'$'}ea31
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uword @shared ww = plot(lsb(xx), msb(xx))
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}
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inline asmsub plot(uword plotx @R0, uword ploty @R1) -> uword @AY{
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%asm {{
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lda cx16.r0
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ldy cx16.r1
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rts
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}}
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}
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}"""
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compileText(C64Target, true, text, writeAssembly = true).assertSuccess()
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}
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})
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@ -338,7 +338,7 @@ class TypecastExpression(var expression: Expression, var type: DataType, val imp
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expression.linkParents(this)
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}
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override val isSimple = false
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override val isSimple = expression.isSimple
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override fun replaceChildNode(node: Node, replacement: Node) {
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require(replacement is Expression && node===expression)
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@ -3,6 +3,22 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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fix the value of ww being wrong (with optimizations enabled) in :
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sub start() {
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byte ub1 = -50
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byte ub2 = -51
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byte ub3 = -52
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byte ub4 = -53
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word ww = func(ub1, ub2, ub3, ub4)
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txt.print_w(ww)
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}
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sub func(word x1, word y1, word x2, word y2) -> word {
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return x1
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}
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- optimize w=msb(w), w=lsb(w)
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...
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@ -22,7 +38,6 @@ Blocked by an official Commander-x16 r39 release
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Future Things and Ideas
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^^^^^^^^^^^^^^^^^^^^^^^
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- nameInAssemblyCode() should search smarter
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- Typecastexpression.isSimple: make it 'expression.isSimple' rather than always false. (this breaks some things atm)
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- IdentifierReference: fix equality to also include position. CallGraph can then also only store IdentifierRef instead of pair(ident, position) as keys.
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- Fix: don't report as recursion if code assigns address of its own subroutine to something, rather than calling it
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- allow "xxx" * constexpr (where constexpr is not a number literal, now gives expression error not same type)
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@ -43,9 +43,9 @@ main {
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for pixelxb in 0 to 255 {
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pixelyw = cos16u(pixelxb) / 1024 + 120
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graphics.plot(pixelxb, lsb(pixelyw))
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graphics.plot(pixelxb, pixelyw)
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pixelyw = sin16u(pixelxb) / 1024 + 120
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graphics.plot(pixelxb, lsb(pixelyw))
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graphics.plot(pixelxb, pixelyw)
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}
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}
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@ -65,9 +65,9 @@ main {
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for pixelxb in 0 to 179 {
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pixelyw = cosr16u(pixelxb) / 1024 + 120
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graphics.plot(pixelxb, lsb(pixelyw))
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graphics.plot(pixelxb, pixelyw)
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pixelyw = sinr16u(pixelxb) / 1024 + 120
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graphics.plot(pixelxb, lsb(pixelyw))
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graphics.plot(pixelxb, pixelyw)
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}
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}
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@ -4,19 +4,20 @@
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main {
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sub start() {
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str s1 = "irmen"
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ubyte ff = 1
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txt.print(&s1+ff)
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txt.nl()
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txt.print(&s1+ff)
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txt.nl()
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txt.print_uwhex(&s1+ff, true)
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uword xx=$ea31
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xx = lsb(xx)
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uword ww = plot(lsb(xx), msb(xx))
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ww=msb(ww)
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txt.print_uwhex(ww, true)
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}
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inline asmsub plot(uword plotx @R0, uword ploty @R1) -> uword @AY{
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%asm {{
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lda cx16.r0
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ldy cx16.r1
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rts
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}}
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}
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ubyte[] array = [1,2,3,4]
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txt.print_uwhex(&array+ff, true)
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txt.nl()
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txt.print_uwhex(&array+ff, true)
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txt.nl()
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}
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}
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