ir: get rid of '_' symbol prefix

This commit is contained in:
Irmen de Jong 2022-11-03 20:17:55 +01:00
parent 562d722ad5
commit 6f67fc0e02
6 changed files with 32 additions and 31 deletions

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@ -257,6 +257,8 @@ class IRCodeGen(
sub.retvalRegisters, sub.retvalRegisters,
sub.inline, sub.inline,
sub.position) sub.position)
if(sub.children.isNotEmpty())
renamedSub.add(sub.children.single()) renamedSub.add(sub.children.single())
parent.children.remove(sub) parent.children.remove(sub)
parent.add(renamedSub) parent.add(renamedSub)
@ -1091,6 +1093,11 @@ class IRCodeGen(
irBlock += sub irBlock += sub
} }
is PtAsmSub -> { is PtAsmSub -> {
if(child.address!=null) {
// romsub. No codegen needed: calls to this are jumping straight to the address.
require(child.children.isEmpty())
} else {
// regular asmsub
val assemblyChild = child.children.single() as PtInlineAssembly val assemblyChild = child.children.single() as PtInlineAssembly
val asmChunk = IRInlineAsmChunk( val asmChunk = IRInlineAsmChunk(
child.name, assemblyChild.assembly, assemblyChild.isIR, null child.name, assemblyChild.assembly, assemblyChild.isIR, null
@ -1105,6 +1112,7 @@ class IRCodeGen(
child.position child.position
) )
} }
}
is PtInlineAssembly -> { is PtInlineAssembly -> {
irBlock += IRInlineAsmChunk(null, child.assembly, child.isIR, null) irBlock += IRInlineAsmChunk(null, child.assembly, child.isIR, null)
} }

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@ -3,9 +3,6 @@ TODO
For next release For next release
^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^
- ir: get rid of '_' label prefix?
- fix expericodegen (ir code gen for regular cx16 target)
... ...
@ -21,7 +18,12 @@ Future Things and Ideas
Compiler: Compiler:
- create BSS section in output program and put StStaticVariables in there with bss=true. Don't forget to add init code to zero out everything that was put in bss. If array in bss->only zero ONCE! So requires self-modifying code - create BSS section in output program and put StStaticVariables in there with bss=true. Don't forget to add init code to zero out everything that was put in bss. If array in bss->only zero ONCE! So requires self-modifying code
- ir: mechanism to determine for chunks which registers are getting input values from "outside"
- ir: mechanism to determine for chunks which registers are passing values out? (i.e. are used again in another chunk)
- ir: peephole opt: renumber registers in chunks to start with 1 again every time (but keep entry values in mind!)
- ir peephole opt: reuse registers in chunks (but keep result registers in mind that pass values out!)
- ir: add more optimizations in IRPeepholeOptimizer - ir: add more optimizations in IRPeepholeOptimizer
- ir: write addresses as hex into p8ir file
- see if we can let for loops skip the loop if end<start, like other programming languages. Without adding a lot of code size/duplicating the loop condition. - see if we can let for loops skip the loop if end<start, like other programming languages. Without adding a lot of code size/duplicating the loop condition.
this is documented behavior to now loop around but it's too easy to forget about! this is documented behavior to now loop around but it's too easy to forget about!
Lot of work because of so many special cases in ForLoopsAsmgen..... Lot of work because of so many special cases in ForLoopsAsmgen.....

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@ -815,10 +815,7 @@ data class IRInstruction(
result.add(",") result.add(",")
} }
labelSymbol?.let { labelSymbol?.let {
if(it.startsWith('&')) result.add(it)
result.add(it) // address-of something
else
result.add("_$it")
} }
if(result.last() == ",") if(result.last() == ",")
result.removeLast() result.removeLast()

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@ -269,7 +269,7 @@ class IRAsmSubroutine(
private val registersUsed by lazy { registersUsedInAssembly(asmChunk.isIR, asmChunk.assembly) } private val registersUsed by lazy { registersUsedInAssembly(asmChunk.isIR, asmChunk.assembly) }
fun usedRegisters() = registersUsed fun usedRegisters() = registersUsed
fun isEmpty(): Boolean = asmChunk.isEmpty() fun isEmpty(): Boolean = if(address==null) asmChunk.isEmpty() else false
} }
sealed class IRCodeChunkBase(val label: String?, var next: IRCodeChunkBase?) { sealed class IRCodeChunkBase(val label: String?, var next: IRCodeChunkBase?) {

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@ -125,12 +125,7 @@ fun parseIRCodeLine(line: String, location: Pair<IRCodeChunk, Int>?, placeholder
var labelSymbol: String? = null var labelSymbol: String? = null
fun parseValueOrPlaceholder(operand: String, location: Pair<IRCodeChunk, Int>?, rest: String, restIndex: Int): Float? { fun parseValueOrPlaceholder(operand: String, location: Pair<IRCodeChunk, Int>?, rest: String, restIndex: Int): Float? {
return if(operand.startsWith('_')) { return if(operand[0].isLetter()) {
labelSymbol = rest.split(",")[restIndex].trim().drop(1)
if(location!=null)
placeholders[location] = labelSymbol!!
null
} else if(operand[0].isLetter()) {
labelSymbol = rest.split(",")[restIndex].trim() labelSymbol = rest.split(",")[restIndex].trim()
if(location!=null) if(location!=null)
placeholders[location] = labelSymbol!! placeholders[location] = labelSymbol!!
@ -229,8 +224,7 @@ fun parseIRCodeLine(line: String, location: Pair<IRCodeChunk, Int>?, placeholder
floatValue = value floatValue = value
if(opcode in OpcodesForCpuRegisters) { if(opcode in OpcodesForCpuRegisters) {
val regStr = rest.split(',').last().lowercase().trim() val reg = rest.split(',').last().lowercase().trim()
val reg = if(regStr.startsWith('_')) regStr.substring(1) else regStr
if(reg !in setOf( if(reg !in setOf(
"a", "x", "y", "a", "x", "y",
"ax", "ay", "xy", "ax", "ay", "xy",

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@ -43,7 +43,7 @@ class TestInstructions: FunSpec({
ins.reg2 shouldBe null ins.reg2 shouldBe null
ins.value shouldBe null ins.value shouldBe null
ins.labelSymbol shouldBe "a.b.c" ins.labelSymbol shouldBe "a.b.c"
ins.toString() shouldBe "bz.w r11,_a.b.c" ins.toString() shouldBe "bz.w r11,a.b.c"
} }
test("with output registers") { test("with output registers") {