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ir: get rid of '_' symbol prefix
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562d722ad5
commit
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@ -257,6 +257,8 @@ class IRCodeGen(
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sub.retvalRegisters,
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sub.inline,
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sub.position)
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if(sub.children.isNotEmpty())
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renamedSub.add(sub.children.single())
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parent.children.remove(sub)
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parent.add(renamedSub)
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@ -1091,6 +1093,11 @@ class IRCodeGen(
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irBlock += sub
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}
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is PtAsmSub -> {
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if(child.address!=null) {
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// romsub. No codegen needed: calls to this are jumping straight to the address.
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require(child.children.isEmpty())
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} else {
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// regular asmsub
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val assemblyChild = child.children.single() as PtInlineAssembly
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val asmChunk = IRInlineAsmChunk(
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child.name, assemblyChild.assembly, assemblyChild.isIR, null
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@ -1105,6 +1112,7 @@ class IRCodeGen(
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child.position
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)
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}
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}
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is PtInlineAssembly -> {
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irBlock += IRInlineAsmChunk(null, child.assembly, child.isIR, null)
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}
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@ -3,9 +3,6 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- ir: get rid of '_' label prefix?
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- fix expericodegen (ir code gen for regular cx16 target)
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...
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@ -21,7 +18,12 @@ Future Things and Ideas
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Compiler:
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- create BSS section in output program and put StStaticVariables in there with bss=true. Don't forget to add init code to zero out everything that was put in bss. If array in bss->only zero ONCE! So requires self-modifying code
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- ir: mechanism to determine for chunks which registers are getting input values from "outside"
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- ir: mechanism to determine for chunks which registers are passing values out? (i.e. are used again in another chunk)
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- ir: peephole opt: renumber registers in chunks to start with 1 again every time (but keep entry values in mind!)
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- ir peephole opt: reuse registers in chunks (but keep result registers in mind that pass values out!)
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- ir: add more optimizations in IRPeepholeOptimizer
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- ir: write addresses as hex into p8ir file
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- see if we can let for loops skip the loop if end<start, like other programming languages. Without adding a lot of code size/duplicating the loop condition.
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this is documented behavior to now loop around but it's too easy to forget about!
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Lot of work because of so many special cases in ForLoopsAsmgen.....
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@ -815,10 +815,7 @@ data class IRInstruction(
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result.add(",")
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}
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labelSymbol?.let {
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if(it.startsWith('&'))
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result.add(it) // address-of something
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else
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result.add("_$it")
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result.add(it)
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}
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if(result.last() == ",")
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result.removeLast()
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@ -269,7 +269,7 @@ class IRAsmSubroutine(
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private val registersUsed by lazy { registersUsedInAssembly(asmChunk.isIR, asmChunk.assembly) }
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fun usedRegisters() = registersUsed
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fun isEmpty(): Boolean = asmChunk.isEmpty()
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fun isEmpty(): Boolean = if(address==null) asmChunk.isEmpty() else false
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}
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sealed class IRCodeChunkBase(val label: String?, var next: IRCodeChunkBase?) {
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@ -125,12 +125,7 @@ fun parseIRCodeLine(line: String, location: Pair<IRCodeChunk, Int>?, placeholder
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var labelSymbol: String? = null
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fun parseValueOrPlaceholder(operand: String, location: Pair<IRCodeChunk, Int>?, rest: String, restIndex: Int): Float? {
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return if(operand.startsWith('_')) {
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labelSymbol = rest.split(",")[restIndex].trim().drop(1)
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if(location!=null)
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placeholders[location] = labelSymbol!!
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null
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} else if(operand[0].isLetter()) {
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return if(operand[0].isLetter()) {
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labelSymbol = rest.split(",")[restIndex].trim()
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if(location!=null)
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placeholders[location] = labelSymbol!!
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@ -229,8 +224,7 @@ fun parseIRCodeLine(line: String, location: Pair<IRCodeChunk, Int>?, placeholder
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floatValue = value
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if(opcode in OpcodesForCpuRegisters) {
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val regStr = rest.split(',').last().lowercase().trim()
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val reg = if(regStr.startsWith('_')) regStr.substring(1) else regStr
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val reg = rest.split(',').last().lowercase().trim()
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if(reg !in setOf(
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"a", "x", "y",
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"ax", "ay", "xy",
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@ -43,7 +43,7 @@ class TestInstructions: FunSpec({
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ins.reg2 shouldBe null
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ins.value shouldBe null
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ins.labelSymbol shouldBe "a.b.c"
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ins.toString() shouldBe "bz.w r11,_a.b.c"
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ins.toString() shouldBe "bz.w r11,a.b.c"
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}
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test("with output registers") {
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