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https://github.com/irmen/prog8.git
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cleanup of cx16 regs lists
This commit is contained in:
Irmen de Jong
parent
b91aabd3c0
commit
9002c67639
@ -151,7 +151,7 @@ val ElementArrayTypes = mapOf(
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DataType.UWORD to DataType.ARRAY_UW,
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DataType.FLOAT to DataType.ARRAY_F
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)
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val Cx16VirtualRegisters = setOf(RegisterOrPair.R0, RegisterOrPair.R1, RegisterOrPair.R2, RegisterOrPair.R3,
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val Cx16VirtualRegisters = listOf(RegisterOrPair.R0, RegisterOrPair.R1, RegisterOrPair.R2, RegisterOrPair.R3,
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RegisterOrPair.R4, RegisterOrPair.R5, RegisterOrPair.R6, RegisterOrPair.R7,
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RegisterOrPair.R8, RegisterOrPair.R9, RegisterOrPair.R10, RegisterOrPair.R11,
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RegisterOrPair.R12, RegisterOrPair.R13, RegisterOrPair.R14, RegisterOrPair.R15)
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@ -59,7 +59,8 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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}
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}
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else -> {
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// Risk of clobbering due to complex expression args. Work via the evaluation stack.
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// Risk of clobbering due to complex expression args. Evaluate first, then assign registers.
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// TODO not used yet because code is larger: registerArgsViaVirtualRegistersEvaluation(stmt, sub)
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registerArgsViaStackEvaluation(stmt, sub)
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}
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}
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@ -75,6 +76,96 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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}
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}
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private fun registerArgsViaVirtualRegistersEvaluation(stmt: IFunctionCall, sub: Subroutine) {
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// This is called when one or more of the arguments are 'complex' and
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// cannot be assigned to a cpu register easily or risk clobbering other cpu registers.
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// To solve this, the expressions are first evaluated into the 'virtual registers and then loaded from there.
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// TODO not used yet; code generated here is bigger than the eval-stack based code because it always treats the virtual regs as words and also sometimes uses the stack for evaluation and then copies it to a virtual register.
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if(sub.parameters.isEmpty())
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return
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// 1. load all arguments left-to-right into the R0..R15 registers
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for (vrarg in stmt.args.zip(Cx16VirtualRegisters)) {
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asmgen.assignExpressionToRegister(vrarg.first, vrarg.second)
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}
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// 2. Gather up the arguments in the correct registers (in specific order to not clobber earlier values)
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var argForCarry: IndexedValue<Pair<Expression, RegisterOrStatusflag>>? = null
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var argForXregister: IndexedValue<Pair<Expression, RegisterOrStatusflag>>? = null
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var argForAregister: IndexedValue<Pair<Expression, RegisterOrStatusflag>>? = null
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for(argi in stmt.args.zip(sub.asmParameterRegisters).withIndex()) {
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val valueIsInVirtualReg = Cx16VirtualRegisters[argi.index]
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val valueIsInVirtualRegAsmString = valueIsInVirtualReg.toString().toLowerCase()
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when {
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argi.value.second.statusflag == Statusflag.Pc -> {
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require(argForCarry == null)
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argForCarry = argi
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}
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argi.value.second.statusflag != null -> throw AssemblyError("can only use Carry as status flag parameter")
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argi.value.second.registerOrPair in setOf(RegisterOrPair.X, RegisterOrPair.AX, RegisterOrPair.XY) -> {
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require(argForXregister==null)
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argForXregister = argi
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}
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argi.value.second.registerOrPair in setOf(RegisterOrPair.A, RegisterOrPair.AY) -> {
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require(argForAregister == null)
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argForAregister = argi
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}
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argi.value.second.registerOrPair == RegisterOrPair.Y -> {
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asmgen.out(" ldy cx16.$valueIsInVirtualRegAsmString")
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}
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argi.value.second.registerOrPair in Cx16VirtualRegisters -> {
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if(argi.value.second.registerOrPair != valueIsInVirtualReg) {
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asmgen.out("""
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lda cx16.$valueIsInVirtualRegAsmString
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}
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lda cx16.$valueIsInVirtualRegAsmString+1
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}+1
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""")
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}
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}
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else -> throw AssemblyError("weird argument")
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}
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}
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if(argForCarry!=null) {
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asmgen.out("""
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lda cx16.${Cx16VirtualRegisters[argForCarry.index].toString().toLowerCase()}
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beq +
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sec
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bcs ++
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+ clc
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+ php""") // push the status flags
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}
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if(argForAregister!=null) {
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when(argForAregister.value.second.registerOrPair) {
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RegisterOrPair.A -> asmgen.out(" lda cx16.${Cx16VirtualRegisters[argForAregister.index].toString().toLowerCase()}")
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RegisterOrPair.AY -> asmgen.out(" lda cx16.${Cx16VirtualRegisters[argForAregister.index].toString().toLowerCase()} | ldy cx16.${Cx16VirtualRegisters[argForAregister.index].toString().toLowerCase()}+1")
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else -> throw AssemblyError("weird arg")
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}
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}
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if(argForXregister!=null) {
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if(argForAregister!=null)
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asmgen.out(" pha")
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when(argForXregister.value.second.registerOrPair) {
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RegisterOrPair.X -> asmgen.out(" ldx cx16.${Cx16VirtualRegisters[argForXregister.index].toString().toLowerCase()}")
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RegisterOrPair.AX -> asmgen.out(" lda cx16.${Cx16VirtualRegisters[argForXregister.index].toString().toLowerCase()} | ldx cx16.${Cx16VirtualRegisters[argForXregister.index].toString().toLowerCase()}+1")
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RegisterOrPair.XY -> asmgen.out(" ldx cx16.${Cx16VirtualRegisters[argForXregister.index].toString().toLowerCase()} | ldy cx16.${Cx16VirtualRegisters[argForXregister.index].toString().toLowerCase()}+1")
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else -> throw AssemblyError("weird arg")
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}
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if(argForAregister!=null)
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asmgen.out(" pla")
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}
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if(argForCarry!=null)
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asmgen.out(" plp") // set the carry flag back to correct value
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}
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private fun registerArgsViaStackEvaluation(stmt: IFunctionCall, sub: Subroutine) {
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// this is called when one or more of the arguments are 'complex' and
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// cannot be assigned to a register easily or risk clobbering other registers.
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@ -710,22 +710,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.Y -> asmgen.out(" inx | ldy P8ESTACK_LO,x")
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RegisterOrPair.AX -> asmgen.out(" inx | lda P8ESTACK_LO,x | ldx #0")
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RegisterOrPair.AY -> asmgen.out(" inx | lda P8ESTACK_LO,x | ldy #0")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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inx
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lda P8ESTACK_LO,x
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@ -742,22 +727,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.AY-> asmgen.out(" inx | lda P8ESTACK_LO,x | ldy P8ESTACK_HI,x")
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RegisterOrPair.XY-> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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inx
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lda P8ESTACK_LO,x
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@ -806,22 +776,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> asmgen.out(" lda #<$sourceName | ldx #>$sourceName")
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RegisterOrPair.AY -> asmgen.out(" lda #<$sourceName | ldy #>$sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldx #<$sourceName | ldy #>$sourceName")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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lda #<$sourceName
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sta cx16.${target.register.toString().toLowerCase()}
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@ -962,22 +917,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName | ldx $sourceName+1")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy $sourceName+1")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy $sourceName+1")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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lda $sourceName
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sta cx16.${target.register.toString().toLowerCase()}
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@ -1150,22 +1090,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy #0")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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lda $sourceName
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sta cx16.${target.register.toString().toLowerCase()}
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@ -1173,6 +1098,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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sta cx16.${target.register.toString().toLowerCase()}+1
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""")
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}
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else -> throw AssemblyError("weird register")
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}
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}
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TargetStorageKind.STACK -> {
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@ -1295,7 +1221,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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internal fun assignRegisterByte(target: AsmAssignTarget, register: CpuRegister) {
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require(target.datatype in ByteDatatypes)
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if(target.register !in Cx16VirtualRegisters)
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require(target.datatype in ByteDatatypes)
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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asmgen.out(" st${register.name.toLowerCase()} ${target.asmVarname}")
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@ -1330,28 +1258,11 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> { asmgen.out(" ldx #0") }
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RegisterOrPair.XY -> { asmgen.out(" tax | ldy #0") }
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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asmgen.out("""
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sta cx16.${target.register.toString().toLowerCase()}
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ldy #0
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sty cx16.${target.register.toString().toLowerCase()}+1
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""")
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in Cx16VirtualRegisters -> {
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// only assign a single byte to the virtual register's Lsb
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asmgen.out(" sta cx16.${target.register.toString().toLowerCase()}")
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}
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else -> throw AssemblyError("weird register")
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}
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CpuRegister.X -> when(target.register!!) {
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RegisterOrPair.A -> { asmgen.out(" txa") }
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@ -1361,28 +1272,11 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> { asmgen.out(" txa | ldx #0") }
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RegisterOrPair.XY -> { asmgen.out(" ldy #0") }
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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asmgen.out("""
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stx cx16.${target.register.toString().toLowerCase()}
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lda #0
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sta cx16.${target.register.toString().toLowerCase()}+1
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""")
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in Cx16VirtualRegisters -> {
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// only assign a single byte to the virtual register's Lsb
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asmgen.out(" stx cx16.${target.register.toString().toLowerCase()}")
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}
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else -> throw AssemblyError("weird register")
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}
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CpuRegister.Y -> when(target.register!!) {
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RegisterOrPair.A -> { asmgen.out(" tya") }
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@ -1392,27 +1286,11 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AX -> { asmgen.out(" tya | ldx #0") }
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RegisterOrPair.XY -> { asmgen.out(" tya | tax | ldy #0") }
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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asmgen.out("""
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sty cx16.${target.register.toString().toLowerCase()}
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lda #0
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sta cx16.${target.register.toString().toLowerCase()}+1
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""") }
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in Cx16VirtualRegisters -> {
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// only assign a single byte to the virtual register's Lsb
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asmgen.out(" sty cx16.${target.register.toString().toLowerCase()}")
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}
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else -> throw AssemblyError("weird register")
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}
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}
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}
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@ -1472,22 +1350,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AY -> { asmgen.out(" stx P8ZP_SCRATCH_REG | ldy P8ZP_SCRATCH_REG") }
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RegisterOrPair.AX -> { }
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RegisterOrPair.XY -> { asmgen.out(" stx P8ZP_SCRATCH_REG | ldy P8ZP_SCRATCH_REG | tax") }
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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sta cx16.${target.register.toString().toLowerCase()}
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stx cx16.${target.register.toString().toLowerCase()}+1
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@ -1499,22 +1362,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.AY -> { }
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RegisterOrPair.AX -> { asmgen.out(" sty P8ZP_SCRATCH_REG | ldx P8ZP_SCRATCH_REG") }
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RegisterOrPair.XY -> { asmgen.out(" tax") }
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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RegisterOrPair.R3,
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RegisterOrPair.R4,
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RegisterOrPair.R5,
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RegisterOrPair.R6,
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RegisterOrPair.R7,
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RegisterOrPair.R8,
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RegisterOrPair.R9,
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RegisterOrPair.R10,
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RegisterOrPair.R11,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
sta cx16.${target.register.toString().toLowerCase()}
|
||||
sty cx16.${target.register.toString().toLowerCase()}+1
|
||||
@ -1526,22 +1374,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AY -> { asmgen.out(" txa") }
|
||||
RegisterOrPair.AX -> { asmgen.out(" txa | sty P8ZP_SCRATCH_REG | ldx P8ZP_SCRATCH_REG") }
|
||||
RegisterOrPair.XY -> { }
|
||||
RegisterOrPair.R0,
|
||||
RegisterOrPair.R1,
|
||||
RegisterOrPair.R2,
|
||||
RegisterOrPair.R3,
|
||||
RegisterOrPair.R4,
|
||||
RegisterOrPair.R5,
|
||||
RegisterOrPair.R6,
|
||||
RegisterOrPair.R7,
|
||||
RegisterOrPair.R8,
|
||||
RegisterOrPair.R9,
|
||||
RegisterOrPair.R10,
|
||||
RegisterOrPair.R11,
|
||||
RegisterOrPair.R12,
|
||||
RegisterOrPair.R13,
|
||||
RegisterOrPair.R14,
|
||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
stx cx16.${target.register.toString().toLowerCase()}
|
||||
sty cx16.${target.register.toString().toLowerCase()}+1
|
||||
@ -1586,10 +1419,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AX -> asmgen.out(" lda #0 | tax")
|
||||
RegisterOrPair.AY -> asmgen.out(" lda #0 | tay")
|
||||
RegisterOrPair.XY -> asmgen.out(" ldx #0 | ldy #0")
|
||||
RegisterOrPair.R0, RegisterOrPair.R1, RegisterOrPair.R2, RegisterOrPair.R3,
|
||||
RegisterOrPair.R4, RegisterOrPair.R5, RegisterOrPair.R6, RegisterOrPair.R7,
|
||||
RegisterOrPair.R8, RegisterOrPair.R9, RegisterOrPair.R10, RegisterOrPair.R11,
|
||||
RegisterOrPair.R12, RegisterOrPair.R13, RegisterOrPair.R14, RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out(" stz cx16.${target.register.toString().toLowerCase()} | stz cx16.${target.register.toString().toLowerCase()}+1")
|
||||
}
|
||||
else -> throw AssemblyError("invalid register for word value")
|
||||
@ -1639,10 +1469,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AX -> asmgen.out(" lda #<${word.toHex()} | ldx #>${word.toHex()}")
|
||||
RegisterOrPair.AY -> asmgen.out(" lda #<${word.toHex()} | ldy #>${word.toHex()}")
|
||||
RegisterOrPair.XY -> asmgen.out(" ldx #<${word.toHex()} | ldy #>${word.toHex()}")
|
||||
RegisterOrPair.R0, RegisterOrPair.R1, RegisterOrPair.R2, RegisterOrPair.R3,
|
||||
RegisterOrPair.R4, RegisterOrPair.R5, RegisterOrPair.R6, RegisterOrPair.R7,
|
||||
RegisterOrPair.R8, RegisterOrPair.R9, RegisterOrPair.R10, RegisterOrPair.R11,
|
||||
RegisterOrPair.R12, RegisterOrPair.R13, RegisterOrPair.R14, RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
lda #<${word.toHex()}
|
||||
sta cx16.${target.register.toString().toLowerCase()}
|
||||
@ -1692,24 +1519,10 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AY -> asmgen.out(" lda #0 | tay")
|
||||
RegisterOrPair.XY -> asmgen.out(" ldx #0 | ldy #0")
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
|
||||
RegisterOrPair.R0,
|
||||
RegisterOrPair.R1,
|
||||
RegisterOrPair.R2,
|
||||
RegisterOrPair.R3,
|
||||
RegisterOrPair.R4,
|
||||
RegisterOrPair.R5,
|
||||
RegisterOrPair.R6,
|
||||
RegisterOrPair.R7,
|
||||
RegisterOrPair.R8,
|
||||
RegisterOrPair.R9,
|
||||
RegisterOrPair.R10,
|
||||
RegisterOrPair.R11,
|
||||
RegisterOrPair.R12,
|
||||
RegisterOrPair.R13,
|
||||
RegisterOrPair.R14,
|
||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out(" stz cx16.${target.register.toString().toLowerCase()} | stz cx16.${target.register.toString().toLowerCase()}+1")
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
TargetStorageKind.STACK -> {
|
||||
asmgen.out(" stz P8ESTACK_LO,x | dex")
|
||||
@ -1745,22 +1558,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AY -> asmgen.out(" lda #${byte.toHex()} | ldy #0")
|
||||
RegisterOrPair.XY -> asmgen.out(" ldx #${byte.toHex()} | ldy #0")
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
|
||||
RegisterOrPair.R0,
|
||||
RegisterOrPair.R1,
|
||||
RegisterOrPair.R2,
|
||||
RegisterOrPair.R3,
|
||||
RegisterOrPair.R4,
|
||||
RegisterOrPair.R5,
|
||||
RegisterOrPair.R6,
|
||||
RegisterOrPair.R7,
|
||||
RegisterOrPair.R8,
|
||||
RegisterOrPair.R9,
|
||||
RegisterOrPair.R10,
|
||||
RegisterOrPair.R11,
|
||||
RegisterOrPair.R12,
|
||||
RegisterOrPair.R13,
|
||||
RegisterOrPair.R14,
|
||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
lda #${byte.toHex()}
|
||||
sta cx16.${target.register.toString().toLowerCase()}
|
||||
@ -1768,6 +1566,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
sta cx16.${target.register.toString().toLowerCase()}+1
|
||||
""")
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
TargetStorageKind.STACK -> {
|
||||
asmgen.out("""
|
||||
@ -1937,22 +1736,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AY -> asmgen.out(" lda ${address.toHex()} | ldy #0")
|
||||
RegisterOrPair.XY -> asmgen.out(" ldy ${address.toHex()} | ldy #0")
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
|
||||
RegisterOrPair.R0,
|
||||
RegisterOrPair.R1,
|
||||
RegisterOrPair.R2,
|
||||
RegisterOrPair.R3,
|
||||
RegisterOrPair.R4,
|
||||
RegisterOrPair.R5,
|
||||
RegisterOrPair.R6,
|
||||
RegisterOrPair.R7,
|
||||
RegisterOrPair.R8,
|
||||
RegisterOrPair.R9,
|
||||
RegisterOrPair.R10,
|
||||
RegisterOrPair.R11,
|
||||
RegisterOrPair.R12,
|
||||
RegisterOrPair.R13,
|
||||
RegisterOrPair.R14,
|
||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
lda ${address.toHex()}
|
||||
sta cx16.${target.register.toString().toLowerCase()}
|
||||
@ -1960,6 +1744,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
sta cx16.${target.register.toString().toLowerCase()}+1
|
||||
""")
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
TargetStorageKind.STACK -> {
|
||||
asmgen.out("""
|
||||
@ -1991,28 +1776,14 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
RegisterOrPair.AY -> asmgen.out(" ldy #0")
|
||||
RegisterOrPair.XY -> asmgen.out(" tax | ldy #0")
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
|
||||
RegisterOrPair.R0,
|
||||
RegisterOrPair.R1,
|
||||
RegisterOrPair.R2,
|
||||
RegisterOrPair.R3,
|
||||
RegisterOrPair.R4,
|
||||
RegisterOrPair.R5,
|
||||
RegisterOrPair.R6,
|
||||
RegisterOrPair.R7,
|
||||
RegisterOrPair.R8,
|
||||
RegisterOrPair.R9,
|
||||
RegisterOrPair.R10,
|
||||
RegisterOrPair.R11,
|
||||
RegisterOrPair.R12,
|
||||
RegisterOrPair.R13,
|
||||
RegisterOrPair.R14,
|
||||
RegisterOrPair.R15 -> {
|
||||
in Cx16VirtualRegisters -> {
|
||||
asmgen.out("""
|
||||
sta cx16.${target.register.toString().toLowerCase()}
|
||||
lda #0
|
||||
sta cx16.${target.register.toString().toLowerCase()}+1
|
||||
""")
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
}
|
||||
TargetStorageKind.STACK -> {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user