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https://github.com/irmen/prog8.git
synced 2024-11-20 03:32:05 +00:00
don't generate a byte storage for every single time a register needs saving
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parent
7c701bdf3f
commit
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@ -528,32 +528,15 @@ internal class AsmGen(private val program: Program,
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private val saveRegisterLabels = Stack<String>();
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internal fun saveRegister(register: CpuRegister) {
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// TODO use only one saveX label+byte storage per subroutine
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when(register) {
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CpuRegister.A -> out(" pha")
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CpuRegister.X -> {
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if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out(" phx")
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else {
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val save = makeLabel("saveX")
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saveRegisterLabels.push(save)
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out("""
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stx $save
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jmp +
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$save .byte 0
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+""")
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}
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else out(" stx _prog8_regsave${register.name}")
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}
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CpuRegister.Y -> {
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if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out(" phy")
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else {
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val save = makeLabel("saveY")
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saveRegisterLabels.push(save)
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out("""
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sty $save
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jmp +
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$save .byte 0
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+""")
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}
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else out(" sty _prog8_regsave${register.name}")
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}
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}
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}
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@ -563,17 +546,11 @@ $save .byte 0
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CpuRegister.A -> out(" pla")
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CpuRegister.X -> {
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if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out(" plx")
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else {
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val save = saveRegisterLabels.pop()
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out(" ldx $save")
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}
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else out(" ldx _prog8_regsave${register.name}")
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}
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CpuRegister.Y -> {
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if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out(" ply")
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else {
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val save = saveRegisterLabels.pop()
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out(" ldy $save")
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}
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else out(" ldy _prog8_regsave${register.name}")
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}
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}
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}
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@ -783,6 +760,10 @@ $save .byte 0
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out("; statements")
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sub.statements.forEach{ translate(it) }
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out("; variables")
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out("""
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; register saves
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_prog8_regsaveX .byte 0
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_prog8_regsaveY .byte 0""") // TODO only generate these bytes if they're actually used by saveRegister()
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vardecls2asm(sub.statements)
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out(" .pend\n")
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}
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@ -2,6 +2,7 @@
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%import textio
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%import syslib
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%zeropage basicsafe
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%option no_sysinit
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%launcher none
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%address 50000
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@ -1,6 +1,7 @@
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%target c64
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%import textio
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%import syslib
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%option no_sysinit
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%zeropage basicsafe
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; This example shows the directory contents of disk drive 8.
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@ -6,6 +6,22 @@
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main {
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sub start() {
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withX(1)
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withX(2)
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withX(3)
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withY(6)
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withY(7)
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withY(8)
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}
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asmsub withX(ubyte foo @X) {
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%asm {{
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rts
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}}
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}
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asmsub withY(ubyte foo @Y) {
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%asm {{
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rts
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}}
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}
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}
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