diff --git a/compiler/src/prog8/compiler/target/c64/codegen/AsmGen.kt b/compiler/src/prog8/compiler/target/c64/codegen/AsmGen.kt
index b15275dd4..c0b96961d 100644
--- a/compiler/src/prog8/compiler/target/c64/codegen/AsmGen.kt
+++ b/compiler/src/prog8/compiler/target/c64/codegen/AsmGen.kt
@@ -528,32 +528,15 @@ internal class AsmGen(private val program: Program,
     private val saveRegisterLabels = Stack<String>();
 
     internal fun saveRegister(register: CpuRegister) {
-        // TODO use only one saveX label+byte storage per subroutine
         when(register) {
             CpuRegister.A -> out("  pha")
             CpuRegister.X -> {
                 if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out("  phx")
-                else {
-                    val save = makeLabel("saveX")
-                    saveRegisterLabels.push(save)
-                    out("""
-            stx  $save
-            jmp  +
-$save       .byte 0
-+""")
-                }
+                else out("  stx  _prog8_regsave${register.name}")
             }
             CpuRegister.Y -> {
                 if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out("  phy")
-                else {
-                    val save = makeLabel("saveY")
-                    saveRegisterLabels.push(save)
-                    out("""
-            sty  $save
-            jmp  +
-$save       .byte 0
-+""")
-                }
+                else out("  sty  _prog8_regsave${register.name}")
             }
         }
     }
@@ -563,17 +546,11 @@ $save       .byte 0
             CpuRegister.A -> out("  pla")
             CpuRegister.X -> {
                 if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out("  plx")
-                else {
-                    val save = saveRegisterLabels.pop()
-                    out("  ldx  $save")
-                }
+                else out("  ldx  _prog8_regsave${register.name}")
             }
             CpuRegister.Y -> {
                 if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) out("  ply")
-                else {
-                    val save = saveRegisterLabels.pop()
-                    out("  ldy  $save")
-                }
+                else out("  ldy  _prog8_regsave${register.name}")
             }
         }
     }
@@ -783,6 +760,10 @@ $save       .byte 0
             out("; statements")
             sub.statements.forEach{ translate(it) }
             out("; variables")
+            out("""
+                ; register saves
+_prog8_regsaveX     .byte  0                
+_prog8_regsaveY     .byte  0""")        // TODO only generate these bytes if they're actually used by saveRegister()
             vardecls2asm(sub.statements)
             out("  .pend\n")
         }
diff --git a/examples/diskdir-sys50000.p8 b/examples/diskdir-sys50000.p8
index 8afc16bfb..4e9bc93fe 100644
--- a/examples/diskdir-sys50000.p8
+++ b/examples/diskdir-sys50000.p8
@@ -2,6 +2,7 @@
 %import textio
 %import syslib
 %zeropage basicsafe
+%option no_sysinit
 %launcher none
 %address 50000
 
diff --git a/examples/diskdir.p8 b/examples/diskdir.p8
index adcd6386a..0c8b67db7 100644
--- a/examples/diskdir.p8
+++ b/examples/diskdir.p8
@@ -1,6 +1,7 @@
 %target c64
 %import textio
 %import syslib
+%option no_sysinit
 %zeropage basicsafe
 
 ; This example shows the directory contents of disk drive 8.
diff --git a/examples/test.p8 b/examples/test.p8
index b44d613f6..c9006fe99 100644
--- a/examples/test.p8
+++ b/examples/test.p8
@@ -6,6 +6,22 @@
 
 main {
     sub start() {
+        withX(1)
+        withX(2)
+        withX(3)
+        withY(6)
+        withY(7)
+        withY(8)
+    }
 
+    asmsub withX(ubyte foo @X) {
+        %asm {{
+            rts
+        }}
+    }
+    asmsub withY(ubyte foo @Y) {
+        %asm {{
+            rts
+        }}
     }
 }