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fix some split array issues in 6502 codegen
This commit is contained in:
Irmen de Jong
parent
ca60f8ecdd
commit
9896bc110e
@ -362,16 +362,15 @@ class AsmGen6502Internal (
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internal fun loadScaledArrayIndexIntoRegister(
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expr: PtArrayIndexer,
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elementDt: DataType,
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register: CpuRegister,
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addOneExtra: Boolean = false
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register: CpuRegister
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) {
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val reg = register.toString().lowercase()
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val indexnum = expr.index.asConstInteger()
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if (indexnum != null) {
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val indexValue = if(expr.splitWords)
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indexnum + if (addOneExtra) 1 else 0
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indexnum
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else
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indexnum * options.compTarget.memorySize(elementDt) + if (addOneExtra) 1 else 0
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indexnum * options.compTarget.memorySize(elementDt)
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out(" ld$reg #$indexValue")
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return
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}
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@ -382,89 +381,40 @@ class AsmGen6502Internal (
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val indexName = asmVariableName(indexVar)
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if(expr.splitWords) {
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if(addOneExtra) {
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out(" ldy $indexName | iny")
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when (register) {
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CpuRegister.A -> out(" tya")
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CpuRegister.X -> out(" txy")
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CpuRegister.Y -> {}
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}
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} else {
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when (register) {
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CpuRegister.A -> out(" lda $indexName")
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CpuRegister.X -> out(" ldx $indexName")
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CpuRegister.Y -> out(" ldy $indexName")
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}
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when (register) {
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CpuRegister.A -> out(" lda $indexName")
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CpuRegister.X -> out(" ldx $indexName")
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CpuRegister.Y -> out(" ldy $indexName")
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}
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return
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}
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if (addOneExtra) {
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// add 1 to the result
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when (elementDt) {
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in ByteDatatypes -> {
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out(" ldy $indexName | iny")
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when (register) {
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CpuRegister.A -> out(" tya")
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CpuRegister.X -> out(" tyx")
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CpuRegister.Y -> {}
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}
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when (elementDt) {
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in ByteDatatypes -> out(" ld$reg $indexName")
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in WordDatatypes -> {
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out(" lda $indexName | asl a")
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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in WordDatatypes -> {
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out(" lda $indexName | sec | rol a")
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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}
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DataType.FLOAT -> {
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require(options.compTarget.memorySize(DataType.FLOAT) == 5) {"invalid float size ${expr.position}"}
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out(
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"""
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lda $indexName
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asl a
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asl a
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sec
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adc $indexName"""
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)
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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}
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else -> throw AssemblyError("weird dt")
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}
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} else {
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when (elementDt) {
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in ByteDatatypes -> out(" ld$reg $indexName")
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in WordDatatypes -> {
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out(" lda $indexName | asl a")
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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DataType.FLOAT -> {
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require(options.compTarget.memorySize(DataType.FLOAT) == 5) {"invalid float size ${expr.position}"}
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out("""
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lda $indexName
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asl a
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asl a
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clc
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adc $indexName"""
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)
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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DataType.FLOAT -> {
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require(options.compTarget.memorySize(DataType.FLOAT) == 5) {"invalid float size ${expr.position}"}
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out(
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"""
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lda $indexName
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asl a
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asl a
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clc
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adc $indexName"""
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)
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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}
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else -> throw AssemblyError("weird dt")
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}
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else -> throw AssemblyError("weird dt")
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}
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}
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@ -1896,7 +1896,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" inx | lda P8ESTACK_LO,x | sta ${target.asmVarname},y")
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}
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DataType.UWORD, DataType.WORD -> {
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if(target.array!!.splitWords)
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if(target.array.splitWords)
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TODO("assign into split words ${target.position}")
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asmgen.loadScaledArrayIndexIntoRegister(target.array, target.datatype, CpuRegister.Y)
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asmgen.out("""
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@ -2332,7 +2332,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" lda $sourceName | sta ${target.asmVarname}+$scaledIdx")
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}
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else {
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, target.datatype, CpuRegister.Y)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, target.datatype, CpuRegister.Y)
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asmgen.out(" lda $sourceName | sta ${target.asmVarname},y")
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}
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}
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@ -2778,15 +2778,15 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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}
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y, true)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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asmgen.out("""
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pla
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sta ${target.asmVarname}_lsb,y
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sta ${target.asmVarname}_msb,y
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pla
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sta ${target.asmVarname}_msb,y""")
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sta ${target.asmVarname}_lsb,y""")
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} else {
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val srcReg = asmgen.asmSymbolName(regs)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y, true)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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asmgen.out("""
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lda $srcReg
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sta ${target.asmVarname}_lsb,y
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@ -2821,8 +2821,9 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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}
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y, true)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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asmgen.out("""
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iny
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pla
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sta ${target.asmVarname},y
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dey
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@ -2830,8 +2831,9 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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sta ${target.asmVarname},y""")
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} else {
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val srcReg = asmgen.asmSymbolName(regs)
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y, true)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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asmgen.out("""
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iny
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lda $srcReg+1
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sta ${target.asmVarname},y
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dey
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@ -2933,7 +2935,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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TargetStorageKind.ARRAY -> {
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if(target.array!!.splitWords)
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TODO("assign into split words ${target.position}")
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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if(target.array.splitWords)
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asmgen.out("""
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lda #0
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@ -2992,7 +2994,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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TargetStorageKind.ARRAY -> {
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if(target.array!!.splitWords)
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TODO("assign into split words ${target.position}")
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y)
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if(target.array.splitWords)
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asmgen.out("""
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lda #<${word.toHex()}
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@ -3069,7 +3071,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" stz ${target.asmVarname}+$indexValue")
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}
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else {
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UBYTE, CpuRegister.Y)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UBYTE, CpuRegister.Y)
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asmgen.out(" lda #0 | sta ${target.asmVarname},y")
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}
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}
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@ -3127,7 +3129,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" lda #${byte.toHex()} | sta ${target.asmVarname}+$indexValue")
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}
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else {
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asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UBYTE, CpuRegister.Y)
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UBYTE, CpuRegister.Y)
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asmgen.out(" lda #${byte.toHex()} | sta ${target.asmVarname},y")
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}
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}
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@ -171,7 +171,7 @@ psg {
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}
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ubyte[16] envelope_states
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uword[16] envelope_volumes ; scaled by 256
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uword[16] @split envelope_volumes ; scaled by 256
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ubyte[16] envelope_attacks
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ubyte[16] envelope_sustains
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ubyte[16] envelope_releases
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