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IR code blocks now better SSA basic blocks (ending with single branch instruction)

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Irmen de Jong
2025-10-01 19:08:44 +02:00
parent 87c1bbbf40
commit 9d3b2f12fd
8 changed files with 139 additions and 33 deletions
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4
codeGenIntermediate/test/TestVmCodeGen.kt
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@@ -341,7 +341,7 @@ class TestVmCodeGen: FunSpec({
val errors = ErrorReporterForTests()
val result = codegen.generate(program, st, options, errors) as VmAssemblyProgram
val irChunks = (result.irProgram.blocks.first().children.single() as IRSubroutine).chunks
irChunks.size shouldBe 1
irChunks.size shouldBe 2
}
test("integer comparison expressions against zero") {
@@ -537,7 +537,7 @@ class TestVmCodeGen: FunSpec({
val errors = ErrorReporterForTests()
val result = codegen.generate(program, st, options, errors) as VmAssemblyProgram
val irChunks = (result.irProgram.blocks.first().children.single() as IRSubroutine).chunks
irChunks.size shouldBe 1
irChunks.size shouldBe 2
}
test("extsub allowed in ir-codegen") {