mirror of
https://github.com/irmen/prog8.git
synced 2024-09-29 08:57:51 +00:00
optimized codegen for some equality comparison expressions and some logical expressions
This commit is contained in:
Irmen de Jong
parent
90ddec2ad8
commit
a0deb463c9
@ -2874,7 +2874,7 @@ $repeatLabel lda $counterVar
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}
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}
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} else {
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val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, program, this, target.datatype, scope, variableAsmName = asmVariableName(target.scopedName))
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val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, this, target.datatype, scope, variableAsmName = asmVariableName(target.scopedName))
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if (dt in ByteDatatypes) {
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out(" pla")
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assignRegister(RegisterOrPair.A, tgt)
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@ -321,9 +321,9 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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val src = AsmAssignSource(SourceStorageKind.EXPRESSION, program, asmgen, DataType.UWORD, expression = AddressOf(slabname, fcall.position))
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val target =
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if(resultToStack)
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AsmAssignTarget(TargetStorageKind.STACK, program, asmgen, DataType.UWORD, null)
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AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, null)
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else
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AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, null, program, asmgen)
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AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, null, asmgen)
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val assign = AsmAssignment(src, target, false, program.memsizer, fcall.position)
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asmgen.translateNormalAssignment(assign)
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allocations.allocateMemorySlab(name, size, align)
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@ -335,7 +335,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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asmgen.out(" jsr prog8_lib.func_sqrt16_stack")
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else {
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asmgen.out(" jsr prog8_lib.func_sqrt16_into_A")
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, program, asmgen), CpuRegister.A)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
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}
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}
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@ -648,7 +648,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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DataType.FLOAT -> asmgen.out(" jsr floats.func_sign_f_into_A")
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else -> throw AssemblyError("weird type $dt")
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}
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, program, asmgen), CpuRegister.A)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
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}
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}
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@ -669,7 +669,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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DataType.ARRAY_F -> asmgen.out(" jsr floats.func_${function.name}_f_into_A | ldy #0")
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else -> throw AssemblyError("weird type $dt")
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}
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, program, asmgen), CpuRegister.A)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
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}
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}
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@ -692,7 +692,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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DataType.WORD -> asmgen.out(" jsr prog8_lib.abs_w_into_AY")
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else -> throw AssemblyError("weird type")
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}
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assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, scope, program, asmgen), RegisterOrPair.AY)
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assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, scope, asmgen), RegisterOrPair.AY)
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}
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}
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@ -703,7 +703,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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asmgen.out(" jsr prog8_lib.func_rnd_stack")
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else {
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asmgen.out(" jsr math.randbyte")
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, program, asmgen), CpuRegister.A)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
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}
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}
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"rndw" -> {
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@ -711,7 +711,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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asmgen.out(" jsr prog8_lib.func_rndw_stack")
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else {
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asmgen.out(" jsr math.randword")
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assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, scope, program, asmgen), RegisterOrPair.AY)
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assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, scope, asmgen), RegisterOrPair.AY)
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}
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}
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else -> throw AssemblyError("wrong func")
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@ -1084,7 +1084,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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AsmAssignSource.fromAstSource(value, program, asmgen)
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}
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}
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val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, conv.dt, null, variableAsmName = varname)
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val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, conv.dt, null, variableAsmName = varname)
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val assign = AsmAssignment(src, tgt, false, program.memsizer, value.position)
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asmgen.translateNormalAssignment(assign)
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}
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@ -1100,7 +1100,7 @@ internal class BuiltinFunctionsAsmGen(private val program: Program,
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AsmAssignSource.fromAstSource(value, program, asmgen)
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}
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}
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val tgt = AsmAssignTarget.fromRegisters(conv.reg!!, false, null, program, asmgen)
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val tgt = AsmAssignTarget.fromRegisters(conv.reg!!, false, null, asmgen)
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val assign = AsmAssignment(src, tgt, false, program.memsizer, value.position)
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asmgen.translateNormalAssignment(assign)
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}
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@ -234,10 +234,10 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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} else {
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val target: AsmAssignTarget =
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if(parameter.value.type in ByteDatatypes && (register==RegisterOrPair.AX || register == RegisterOrPair.AY || register==RegisterOrPair.XY || register in Cx16VirtualRegisters))
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AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, parameter.value.type, sub, register = register)
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AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, parameter.value.type, sub, register = register)
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else {
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val signed = parameter.value.type == DataType.BYTE || parameter.value.type == DataType.WORD
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AsmAssignTarget.fromRegisters(register, signed, sub, program, asmgen)
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AsmAssignTarget.fromRegisters(register, signed, sub, asmgen)
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}
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val src = if(valueDt in PassByReferenceDatatypes) {
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if(value is IdentifierReference) {
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@ -308,7 +308,7 @@ internal class ProgramAndVarsGen(
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asmgen.out("; simple int arg(s) passed via register(s)")
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if(sub.parameters.size==1) {
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val dt = sub.parameters[0].type
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val target = AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, dt, sub, variableAsmName = sub.parameters[0].name)
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val target = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, sub, variableAsmName = sub.parameters[0].name)
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if(dt in ByteDatatypes)
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asmgen.assignRegister(RegisterOrPair.A, target)
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else
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@ -316,8 +316,8 @@ internal class ProgramAndVarsGen(
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} else {
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require(sub.parameters.size==2)
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// 2 simple byte args, first in A, second in Y
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val target1 = AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, sub.parameters[0].type, sub, variableAsmName = sub.parameters[0].name)
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val target2 = AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, sub.parameters[1].type, sub, variableAsmName = sub.parameters[1].name)
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val target1 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[0].type, sub, variableAsmName = sub.parameters[0].name)
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val target2 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[1].type, sub, variableAsmName = sub.parameters[1].name)
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asmgen.assignRegister(RegisterOrPair.A, target1)
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asmgen.assignRegister(RegisterOrPair.Y, target2)
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}
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@ -29,7 +29,6 @@ internal enum class SourceStorageKind {
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}
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internal class AsmAssignTarget(val kind: TargetStorageKind,
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private val program: Program,
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private val asmgen: AsmGen,
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val datatype: DataType,
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val scope: Subroutine?,
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@ -70,28 +69,28 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
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if(reg.statusflag!=null)
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throw AssemblyError("can't assign value to processor statusflag directly")
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else
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return AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, dt, assign.definingSubroutine, register=reg.registerOrPair, origAstTarget = this)
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return AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, dt, assign.definingSubroutine, register=reg.registerOrPair, origAstTarget = this)
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}
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}
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return AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, dt, assign.definingSubroutine, variableAsmName = asmgen.asmVariableName(identifier!!), origAstTarget = this)
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return AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, assign.definingSubroutine, variableAsmName = asmgen.asmVariableName(identifier!!), origAstTarget = this)
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}
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arrayindexed != null -> return AsmAssignTarget(TargetStorageKind.ARRAY, program, asmgen, dt, assign.definingSubroutine, array = arrayindexed, origAstTarget = this)
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memoryAddress != null -> return AsmAssignTarget(TargetStorageKind.MEMORY, program, asmgen, dt, assign.definingSubroutine, memory = memoryAddress, origAstTarget = this)
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arrayindexed != null -> return AsmAssignTarget(TargetStorageKind.ARRAY, asmgen, dt, assign.definingSubroutine, array = arrayindexed, origAstTarget = this)
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memoryAddress != null -> return AsmAssignTarget(TargetStorageKind.MEMORY, asmgen, dt, assign.definingSubroutine, memory = memoryAddress, origAstTarget = this)
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else -> throw AssemblyError("weird target")
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}
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}
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}
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fun fromRegisters(registers: RegisterOrPair, signed: Boolean, scope: Subroutine?, program: Program, asmgen: AsmGen): AsmAssignTarget =
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fun fromRegisters(registers: RegisterOrPair, signed: Boolean, scope: Subroutine?, asmgen: AsmGen): AsmAssignTarget =
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when(registers) {
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RegisterOrPair.A,
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RegisterOrPair.X,
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RegisterOrPair.Y -> AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, if(signed) DataType.BYTE else DataType.UBYTE, scope, register = registers)
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RegisterOrPair.Y -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.BYTE else DataType.UBYTE, scope, register = registers)
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RegisterOrPair.AX,
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RegisterOrPair.AY,
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RegisterOrPair.XY -> AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
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RegisterOrPair.XY -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
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RegisterOrPair.FAC1,
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RegisterOrPair.FAC2 -> AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, DataType.FLOAT, scope, register = registers)
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RegisterOrPair.FAC2 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.FLOAT, scope, register = registers)
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RegisterOrPair.R0,
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RegisterOrPair.R1,
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RegisterOrPair.R2,
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@ -107,7 +106,7 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
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RegisterOrPair.R12,
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RegisterOrPair.R13,
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RegisterOrPair.R14,
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RegisterOrPair.R15 -> AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
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RegisterOrPair.R15 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
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}
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}
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}
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@ -29,7 +29,7 @@ internal class AssignmentAsmGen(private val program: Program,
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internal fun virtualRegsToVariables(origtarget: AsmAssignTarget): AsmAssignTarget {
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return if(origtarget.kind==TargetStorageKind.REGISTER && origtarget.register in Cx16VirtualRegisters) {
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AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, origtarget.datatype, origtarget.scope,
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AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, origtarget.datatype, origtarget.scope,
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variableAsmName = "cx16.${origtarget.register!!.name.lowercase()}", origAstTarget = origtarget.origAstTarget)
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} else origtarget
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}
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@ -330,135 +330,229 @@ internal class AssignmentAsmGen(private val program: Program,
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if(!expr.inferType(program).isInteger)
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return false
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if(expr.operator!="+" && expr.operator!="-")
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return false
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val dt = expr.inferType(program).getOrElse { throw AssemblyError("invalid dt") }
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val left = expr.left
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val right = expr.right
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if(dt in ByteDatatypes) {
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when (right) {
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is IdentifierReference -> {
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assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
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val symname = asmgen.asmVariableName(right)
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if(expr.operator=="+")
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asmgen.out(" clc | adc $symname")
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else
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asmgen.out(" sec | sbc $symname")
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assignRegisterByte(assign.target, CpuRegister.A)
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return true
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if(expr.operator in setOf("&", "|", "^", "and", "or", "xor")) {
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if(expr.left.inferType(program).isBytes && expr.right.inferType(program).isBytes &&
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expr.left.isSimple && expr.right.isSimple) {
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assignExpressionToRegister(expr.left, RegisterOrPair.A, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_B1", DataType.UBYTE, expr.definingSubroutine)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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when(expr.operator) {
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"&", "and" -> asmgen.out(" and P8ZP_SCRATCH_B1")
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"|", "or" -> asmgen.out(" ora P8ZP_SCRATCH_B1")
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"^", "xor" -> asmgen.out(" eor P8ZP_SCRATCH_B1")
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else -> throw AssemblyError("invalid operator")
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}
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is NumericLiteral -> {
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assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
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if(expr.operator=="+")
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asmgen.out(" clc | adc #${right.number.toHex()}")
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else
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asmgen.out(" sec | sbc #${right.number.toHex()}")
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assignRegisterByte(assign.target, CpuRegister.A)
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return true
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}
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else -> return false
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assignRegisterByte(assign.target, CpuRegister.A)
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return true
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}
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} else if(dt in WordDatatypes) {
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when (right) {
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is AddressOf -> {
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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val symbol = asmgen.asmVariableName(right.identifier)
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if(expr.operator=="+")
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asmgen.out("""
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clc
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adc #<$symbol
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pha
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tya
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adc #>$symbol
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tay
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pla""")
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else
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asmgen.out("""
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sec
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sbc #<$symbol
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pha
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tya
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sbc #>$symbol
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tay
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pla""")
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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return true
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if(expr.left.inferType(program).isWords && expr.right.inferType(program).isWords &&
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expr.left.isSimple && expr.right.isSimple) {
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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asmgen.saveRegisterStack(CpuRegister.Y, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_W1", DataType.UWORD, expr.definingSubroutine)
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when(expr.operator) {
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"&", "and" -> asmgen.out(" pla | and P8ZP_SCRATCH_W1+1 | tay | pla | and P8ZP_SCRATCH_W1")
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"|", "or" -> asmgen.out(" pla | ora P8ZP_SCRATCH_W1+1 | tay | pla | ora P8ZP_SCRATCH_W1")
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"^", "xor" -> asmgen.out(" pla | eor P8ZP_SCRATCH_W1+1 | tay | pla | eor P8ZP_SCRATCH_W1")
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else -> throw AssemblyError("invalid operator")
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}
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is IdentifierReference -> {
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val symname = asmgen.asmVariableName(right)
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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if(expr.operator=="+")
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asmgen.out("""
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clc
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adc $symname
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pha
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tya
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adc $symname+1
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tay
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pla""")
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else
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asmgen.out("""
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sec
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sbc $symname
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pha
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tya
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sbc $symname+1
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tay
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pla""")
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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return true
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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return true
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}
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return false
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}
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if(expr.operator == "==" || expr.operator == "!=") {
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// expression datatype is BOOL (ubyte) but operands can be anything
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if(expr.left.inferType(program).isBytes && expr.right.inferType(program).isBytes &&
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expr.left.isSimple && expr.right.isSimple) {
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assignExpressionToRegister(expr.left, RegisterOrPair.A, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_B1", DataType.UBYTE, expr.definingSubroutine)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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if(expr.operator=="==") {
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asmgen.out("""
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cmp P8ZP_SCRATCH_B1
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bne +
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lda #1
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bne ++
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+ lda #0
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+""")
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} else {
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asmgen.out("""
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cmp P8ZP_SCRATCH_B1
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beq +
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lda #1
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bne ++
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+ lda #0
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+""")
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}
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is NumericLiteral -> {
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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if(expr.operator=="+") {
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asmgen.out("""
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clc
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adc #<${right.number.toHex()}
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pha
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tya
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adc #>${right.number.toHex()}
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tay
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pla""")
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} else if(expr.operator=="-") {
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asmgen.out("""
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sec
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sbc #<${right.number.toHex()}
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pha
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tya
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sbc #>${right.number.toHex()}
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tay
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pla""")
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assignRegisterByte(assign.target, CpuRegister.A)
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return true
|
||||
} else if(expr.left.inferType(program).isWords && expr.right.inferType(program).isWords &&
|
||||
expr.left.isSimple && expr.right.isSimple) {
|
||||
assignExpressionToRegister(expr.left, RegisterOrPair.AY, false)
|
||||
asmgen.saveRegisterStack(CpuRegister.A, false)
|
||||
asmgen.saveRegisterStack(CpuRegister.Y, false)
|
||||
assignExpressionToVariable(expr.right, "P8ZP_SCRATCH_W1", DataType.UWORD, expr.definingSubroutine)
|
||||
asmgen.restoreRegisterStack(CpuRegister.Y, false)
|
||||
asmgen.restoreRegisterStack(CpuRegister.A, false)
|
||||
if(expr.operator=="==") {
|
||||
asmgen.out("""
|
||||
cmp P8ZP_SCRATCH_W1
|
||||
bne +
|
||||
cpy P8ZP_SCRATCH_W1+1
|
||||
bne +
|
||||
lda #1
|
||||
bne ++
|
||||
+ lda #0
|
||||
+""")
|
||||
} else {
|
||||
asmgen.out("""
|
||||
cmp P8ZP_SCRATCH_W1
|
||||
bne +
|
||||
cpy P8ZP_SCRATCH_W1+1
|
||||
bne +
|
||||
lda #0
|
||||
bne ++
|
||||
+ lda #1
|
||||
+""")
|
||||
}
|
||||
assignRegisterByte(assign.target, CpuRegister.A)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
else if(expr.operator=="+" || expr.operator=="-") {
|
||||
val dt = expr.inferType(program).getOrElse { throw AssemblyError("invalid dt") }
|
||||
val left = expr.left
|
||||
val right = expr.right
|
||||
if(dt in ByteDatatypes) {
|
||||
when (right) {
|
||||
is IdentifierReference -> {
|
||||
assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
|
||||
val symname = asmgen.asmVariableName(right)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out(" clc | adc $symname")
|
||||
else
|
||||
asmgen.out(" sec | sbc $symname")
|
||||
assignRegisterByte(assign.target, CpuRegister.A)
|
||||
return true
|
||||
}
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
is NumericLiteral -> {
|
||||
assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out(" clc | adc #${right.number.toHex()}")
|
||||
else
|
||||
asmgen.out(" sec | sbc #${right.number.toHex()}")
|
||||
assignRegisterByte(assign.target, CpuRegister.A)
|
||||
return true
|
||||
}
|
||||
else -> return false
|
||||
}
|
||||
is TypecastExpression -> {
|
||||
val castedValue = right.expression
|
||||
if(right.type in WordDatatypes && castedValue.inferType(program).isBytes) {
|
||||
if(castedValue is IdentifierReference) {
|
||||
val castedSymname = asmgen.asmVariableName(castedValue)
|
||||
assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out("""
|
||||
clc
|
||||
adc $castedSymname
|
||||
bcc +
|
||||
iny
|
||||
+""")
|
||||
else
|
||||
asmgen.out("""
|
||||
sec
|
||||
sbc $castedSymname
|
||||
bcs +
|
||||
dey
|
||||
+""")
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
} else if(dt in WordDatatypes) {
|
||||
when (right) {
|
||||
is AddressOf -> {
|
||||
assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
|
||||
val symbol = asmgen.asmVariableName(right.identifier)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out("""
|
||||
clc
|
||||
adc #<$symbol
|
||||
pha
|
||||
tya
|
||||
adc #>$symbol
|
||||
tay
|
||||
pla""")
|
||||
else
|
||||
asmgen.out("""
|
||||
sec
|
||||
sbc #<$symbol
|
||||
pha
|
||||
tya
|
||||
sbc #>$symbol
|
||||
tay
|
||||
pla""")
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
}
|
||||
is IdentifierReference -> {
|
||||
val symname = asmgen.asmVariableName(right)
|
||||
assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out("""
|
||||
clc
|
||||
adc $symname
|
||||
pha
|
||||
tya
|
||||
adc $symname+1
|
||||
tay
|
||||
pla""")
|
||||
else
|
||||
asmgen.out("""
|
||||
sec
|
||||
sbc $symname
|
||||
pha
|
||||
tya
|
||||
sbc $symname+1
|
||||
tay
|
||||
pla""")
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
}
|
||||
is NumericLiteral -> {
|
||||
assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
|
||||
if(expr.operator=="+") {
|
||||
asmgen.out("""
|
||||
clc
|
||||
adc #<${right.number.toHex()}
|
||||
pha
|
||||
tya
|
||||
adc #>${right.number.toHex()}
|
||||
tay
|
||||
pla""")
|
||||
} else if(expr.operator=="-") {
|
||||
asmgen.out("""
|
||||
sec
|
||||
sbc #<${right.number.toHex()}
|
||||
pha
|
||||
tya
|
||||
sbc #>${right.number.toHex()}
|
||||
tay
|
||||
pla""")
|
||||
}
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
}
|
||||
is TypecastExpression -> {
|
||||
val castedValue = right.expression
|
||||
if(right.type in WordDatatypes && castedValue.inferType(program).isBytes) {
|
||||
if(castedValue is IdentifierReference) {
|
||||
val castedSymname = asmgen.asmVariableName(castedValue)
|
||||
assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
|
||||
if(expr.operator=="+")
|
||||
asmgen.out("""
|
||||
clc
|
||||
adc $castedSymname
|
||||
bcc +
|
||||
iny
|
||||
+""")
|
||||
else
|
||||
asmgen.out("""
|
||||
sec
|
||||
sbc $castedSymname
|
||||
bcs +
|
||||
dey
|
||||
+""")
|
||||
assignRegisterpairWord(assign.target, RegisterOrPair.AY)
|
||||
return true
|
||||
}
|
||||
}
|
||||
}
|
||||
else -> return false
|
||||
}
|
||||
else -> return false
|
||||
}
|
||||
}
|
||||
return false
|
||||
@ -561,7 +655,7 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
val varname = asmgen.asmVariableName(containment.iterable as IdentifierReference)
|
||||
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt istype DataType.BYTE)
|
||||
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingSubroutine!!)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
asmgen.restoreRegisterLocal(CpuRegister.A)
|
||||
asmgen.out(" ldy #${stringVal.value.length}")
|
||||
asmgen.out(" jsr prog8_lib.containment_bytearray")
|
||||
@ -580,14 +674,14 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
in ByteDatatypes -> {
|
||||
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt istype DataType.BYTE)
|
||||
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingSubroutine!!)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
asmgen.restoreRegisterLocal(CpuRegister.A)
|
||||
asmgen.out(" ldy #${arrayVal.value.size}")
|
||||
asmgen.out(" jsr prog8_lib.containment_bytearray")
|
||||
}
|
||||
in WordDatatypes -> {
|
||||
assignExpressionToVariable(containment.element, "P8ZP_SCRATCH_W1", elementDt.getOr(DataType.UNDEFINED), containment.definingSubroutine)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W2"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W2"), varname)
|
||||
asmgen.out(" ldy #${arrayVal.value.size}")
|
||||
asmgen.out(" jsr prog8_lib.containment_wordarray")
|
||||
}
|
||||
@ -604,7 +698,7 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
// use subroutine
|
||||
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt istype DataType.BYTE)
|
||||
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingSubroutine!!)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
asmgen.restoreRegisterLocal(CpuRegister.A)
|
||||
val stringVal = variable.value as StringLiteral
|
||||
asmgen.out(" ldy #${stringVal.value.length}")
|
||||
@ -618,7 +712,7 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
val arrayVal = variable.value as ArrayLiteral
|
||||
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt istype DataType.BYTE)
|
||||
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingSubroutine!!)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W1"), varname)
|
||||
asmgen.restoreRegisterLocal(CpuRegister.A)
|
||||
asmgen.out(" ldy #${arrayVal.value.size}")
|
||||
asmgen.out(" jsr prog8_lib.containment_bytearray")
|
||||
@ -627,7 +721,7 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
DataType.ARRAY_W, DataType.ARRAY_UW -> {
|
||||
val arrayVal = variable.value as ArrayLiteral
|
||||
assignExpressionToVariable(containment.element, "P8ZP_SCRATCH_W1", elementDt.getOr(DataType.UNDEFINED), containment.definingSubroutine)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W2"), varname)
|
||||
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingSubroutine, "P8ZP_SCRATCH_W2"), varname)
|
||||
asmgen.out(" ldy #${arrayVal.value.size}")
|
||||
asmgen.out(" jsr prog8_lib.containment_wordarray")
|
||||
return
|
||||
@ -2579,7 +2673,7 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
|
||||
internal fun assignExpressionToRegister(expr: Expression, register: RegisterOrPair, signed: Boolean) {
|
||||
val src = AsmAssignSource.fromAstSource(expr, program, asmgen)
|
||||
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, program, asmgen)
|
||||
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, asmgen)
|
||||
val assign = AsmAssignment(src, tgt, false, program.memsizer, expr.position)
|
||||
translateNormalAssignment(assign)
|
||||
}
|
||||
@ -2589,14 +2683,14 @@ internal class AssignmentAsmGen(private val program: Program,
|
||||
throw AssemblyError("can't directly assign a FLOAT expression to an integer variable $expr")
|
||||
} else {
|
||||
val src = AsmAssignSource.fromAstSource(expr, program, asmgen)
|
||||
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, program, asmgen, dt, scope, variableAsmName = asmVarName)
|
||||
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, scope, variableAsmName = asmVarName)
|
||||
val assign = AsmAssignment(src, tgt, false, program.memsizer, expr.position)
|
||||
translateNormalAssignment(assign)
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignVariableToRegister(asmVarName: String, register: RegisterOrPair, signed: Boolean) {
|
||||
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, program, asmgen)
|
||||
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, asmgen)
|
||||
val src = AsmAssignSource(SourceStorageKind.VARIABLE, program, asmgen, tgt.datatype, variableAsmName = asmVarName)
|
||||
val assign = AsmAssignment(src, tgt, false, program.memsizer, Position.DUMMY)
|
||||
translateNormalAssignment(assign)
|
||||
|
||||
@ -236,7 +236,7 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
|
||||
}
|
||||
else -> {
|
||||
// TODO use some other evaluation here; don't use the estack to transfer the address to read/write from
|
||||
asmgen.assignExpressionTo(memory.addressExpression, AsmAssignTarget(TargetStorageKind.STACK, program, asmgen, DataType.UWORD, memory.definingSubroutine))
|
||||
asmgen.assignExpressionTo(memory.addressExpression, AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, memory.definingSubroutine))
|
||||
asmgen.out(" jsr prog8_lib.read_byte_from_address_on_stack | sta P8ZP_SCRATCH_B1")
|
||||
when {
|
||||
valueLv != null -> inplaceModification_byte_litval_to_variable("P8ZP_SCRATCH_B1", DataType.UBYTE, operator, valueLv.toInt())
|
||||
@ -305,7 +305,6 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
|
||||
AsmAssignTarget.fromRegisters(
|
||||
RegisterOrPair.A,
|
||||
target.datatype == DataType.BYTE, null,
|
||||
program,
|
||||
asmgen
|
||||
)
|
||||
val assign = AsmAssignment(target.origAssign.source, tgt, false, program.memsizer, value.position)
|
||||
@ -317,7 +316,6 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
|
||||
AsmAssignTarget.fromRegisters(
|
||||
RegisterOrPair.AY,
|
||||
target.datatype == DataType.WORD, null,
|
||||
program,
|
||||
asmgen
|
||||
)
|
||||
val assign = AsmAssignment(target.origAssign.source, tgt, false, program.memsizer, value.position)
|
||||
@ -329,7 +327,6 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
|
||||
AsmAssignTarget.fromRegisters(
|
||||
RegisterOrPair.FAC1,
|
||||
true, null,
|
||||
program,
|
||||
asmgen
|
||||
)
|
||||
val assign = AsmAssignment(target.origAssign.source, tgt, false, program.memsizer, value.position)
|
||||
|
||||
@ -3,8 +3,6 @@ TODO
|
||||
|
||||
For next release
|
||||
^^^^^^^^^^^^^^^^
|
||||
- can we optimize logical expresions such as if input_size and command_line[0]!=159 to not use stack eval anymore?
|
||||
|
||||
...
|
||||
|
||||
|
||||
|
||||
@ -1,26 +1,41 @@
|
||||
%import textio
|
||||
%import string
|
||||
%zeropage kernalsafe
|
||||
%zeropage basicsafe
|
||||
|
||||
main {
|
||||
sub start() {
|
||||
cx16.r0 = $ea31
|
||||
cx16.r15 = $ff99
|
||||
str name = "irmen"
|
||||
bool aa = true
|
||||
ubyte[] bb = [%0000, %1111]
|
||||
uword w1 = %1000000000000001
|
||||
uword w2 = %0000000000000010
|
||||
|
||||
txt.print_uwhex(cx16.r0, true)
|
||||
if aa and w1 | w2
|
||||
txt.print("ok")
|
||||
else
|
||||
txt.print("fail")
|
||||
txt.spc()
|
||||
txt.print_uwhex(cx16.r15, true)
|
||||
txt.nl()
|
||||
cx16.r7 = &name
|
||||
txt.chrout(cx16.r7[0])
|
||||
txt.chrout(cx16.r7[1])
|
||||
txt.chrout(cx16.r7[2])
|
||||
txt.chrout(cx16.r7[3])
|
||||
txt.chrout(cx16.r7[4])
|
||||
txt.nl()
|
||||
|
||||
repeat {
|
||||
}
|
||||
if aa and w1 & w2
|
||||
txt.print("fail")
|
||||
else
|
||||
txt.print("ok")
|
||||
txt.spc()
|
||||
|
||||
if aa and bb[0] | %0100
|
||||
txt.print("ok")
|
||||
else
|
||||
txt.print("fail")
|
||||
txt.spc()
|
||||
|
||||
if aa and bb[0] & %0100
|
||||
txt.print("fail")
|
||||
else
|
||||
txt.print("ok")
|
||||
txt.spc()
|
||||
|
||||
aa = aa and bb[0] | %0100
|
||||
txt.print_ub(aa)
|
||||
txt.spc()
|
||||
aa = aa and bb[0] & %0100
|
||||
txt.print_ub(aa)
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user