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fix long bitwise expressions temp register usage

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Irmen de Jong
2025-10-14 02:57:48 +02:00
parent ee5d33a230
commit a36501a9ed
3 changed files with 14 additions and 21 deletions
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19
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AssignmentAsmGen.kt
View File

@@ -2034,25 +2034,24 @@ internal class AssignmentAsmGen(
}
}
// TODO use R14:R15 instead
val targetreg = target.register
if(targetreg!=RegisterOrPair.R12R13_32) {
asmgen.pushLongRegisters(RegisterOrPair.R12R13_32, 1)
if(targetreg!=RegisterOrPair.R14R15_32) {
asmgen.pushLongRegisters(RegisterOrPair.R14R15_32, 1)
}
asmgen.assignExpressionToRegister(expr.left, RegisterOrPair.R12R13_32, expr.left.type.isSigned)
asmgen.assignExpressionToRegister(expr.left, RegisterOrPair.R14R15_32, expr.left.type.isSigned)
val constval = expr.right.asConstInteger()
val varname = (expr.right as? PtIdentifier)?.name
if(constval!=null)
augmentableAsmGen.inplacemodificationLongWithLiteralval("cx16.r12", expr.operator, constval)
augmentableAsmGen.inplacemodificationLongWithLiteralval("cx16.r14", expr.operator, constval)
else if(varname!=null)
augmentableAsmGen.inplacemodificationLongWithVariable("cx16.r12", expr.operator, varname)
augmentableAsmGen.inplacemodificationLongWithVariable("cx16.r14", expr.operator, varname)
else {
// TODO: preserve R14:R15 on stack here? (the function does't do it for us)
augmentableAsmGen.inplacemodificationLongWithExpression("cx16.r12", expr.operator, expr.right)
augmentableAsmGen.inplacemodificationLongWithExpression("cx16.r14", expr.operator, expr.right)
}
assignRegisterLong(target, RegisterOrPair.R12R13_32)
if(targetreg!=RegisterOrPair.R12R13_32) {
asmgen.popLongRegisters(RegisterOrPair.R12R13_32, 1)
assignRegisterLong(target, RegisterOrPair.R14R15_32)
if(targetreg!=RegisterOrPair.R14R15_32) {
asmgen.popLongRegisters(RegisterOrPair.R14R15_32, 1)
}
return true
}

1
docs/source/todo.rst
View File

@@ -1,7 +1,6 @@
TODO
====
- optimizedBitwiseExpr(): use R14:R15 instead to save copying/stack manipulation?
- implement inplaceLongAdd/Sub in PointerAssignmentGen

15
examples/test.p8
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@@ -7,17 +7,12 @@ main {
sub start() {
long @shared lv, lv2
cx16.r0L = if lv==9999 then 99 else 42
txt.print_ub(cx16.r0L)
txt.nl()
lv = $11111111
lv2 = $55555555
lv2 = if lv==9999 then 999999 else 424242
txt.print_l(lv2)
txt.nl()
lv=9999
lv2 = if lv==9999 then 999999 else 424242
txt.print_l(lv2)
txt.nl()
lv = lv | lv2 ^ 999999
txt.print_ulhex(lv, true) ; $555b177b
; long @shared lv1 = $12345678