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Revert "ir: SCC now sets all bits to 1 (or 0)"
This reverts commit 7245aece4f
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This commit is contained in:
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e98bbc1c52
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@ -1,7 +1,7 @@
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TODO
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TODO
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====
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====
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- IR/VM: fix the vm/textelite game, it now prints garbage! (caused by the SGE opcode implementation change to set -1 instead of 1)
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- VM: fix endless loop n=0 :: for i in 5 downto n (fine for n=1) (wrong for bytes and words)
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- IR: instructions that do type conversion (SZ etc, CONCAT, SGN) should put the result in a DIFFERENT register.
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- IR: instructions that do type conversion (SZ etc, CONCAT, SGN) should put the result in a DIFFERENT register.
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@ -97,18 +97,19 @@ bgesr reg1, reg2, address - jump to location in program given by l
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ble reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (unsigned)
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ble reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (unsigned)
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bles reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (signed)
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bles reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (signed)
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( NOTE: there are no bltr/bler instructions because these are equivalent to bgtr/bger with the register operands swapped around.)
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( NOTE: there are no bltr/bler instructions because these are equivalent to bgtr/bger with the register operands swapped around.)
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sz reg1, reg2 - set reg1=-1 (all bits one) if reg2==0, else 0
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sz reg1, reg2 - set reg1=1 if reg2==0, else 0
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snz reg1, reg2 - set reg1=-1 (all bits one) if reg2!=0, else 0
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snz reg1, reg2 - set reg1=1 if reg2!=0, else 0
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seq reg1, reg2 - set reg1=-1 (all bits one) if reg1 == reg2, else 0
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seq reg1, reg2 - set reg1=1 if reg1 == reg2, else 0
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sne reg1, reg2 - set reg1=-1 (all bits one) if reg1 != reg2, else 0
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sne reg1, reg2 - set reg1=1 if reg1 != reg2, else 0
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slt reg1, reg2 - set reg1=-1 (all bits one) if reg1 < reg2 (unsigned), else 0
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slt reg1, reg2 - set reg1=1 if reg1 < reg2 (unsigned), else 0
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slts reg1, reg2 - set reg1=-1 (all bits one) if reg1 < reg2 (signed), else 0
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slts reg1, reg2 - set reg1=1 if reg1 < reg2 (signed), else 0
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sle reg1, reg2 - set reg1=-1 (all bits one) if reg1 <= reg2 (unsigned), else 0
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sle reg1, reg2 - set reg1=1 if reg1 <= reg2 (unsigned), else 0
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sles reg1, reg2 - set reg1=-1 (all bits one) if reg1 <= reg2 (signed), else 0
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sles reg1, reg2 - set reg1=1 if reg1 <= reg2 (signed), else 0
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sgt reg1, reg2 - set reg1=-1 (all bits one) if reg1 > reg2 (unsigned), else 0
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sgt reg1, reg2 - set reg1=1 if reg1 > reg2 (unsigned), else 0
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sgts reg1, reg2 - set reg1=-1 (all bits one) if reg1 > reg2 (signed), else 0
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sgts reg1, reg2 - set reg1=1 if reg1 > reg2 (signed), else 0
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sge reg1, reg2 - set reg1=-1 (all bits one) if reg1 >= reg2 (unsigned), else 0
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sge reg1, reg2 - set reg1=1 if reg1 >= reg2 (unsigned), else 0
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sges reg1, reg2 - set reg1=-1 (all bits one) if reg1 >= reg2 (signed), else 0
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sges reg1, reg2 - set reg1=1 if reg1 >= reg2 (signed), else 0
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(note: on the M68k these instructions will set all bits to 1 (so value=-1 instead of 1), but the boolean logic here requires it to be 0 or 1 in this IR)
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ARITHMETIC
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ARITHMETIC
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@ -808,84 +808,84 @@ class VirtualMachine(irProgram: IRProgram) {
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private fun InsSZ(i: IRInstruction) {
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private fun InsSZ(i: IRInstruction) {
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val (_: Int, right: Int) = getSetOnConditionOperands(i)
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val (_: Int, right: Int) = getSetOnConditionOperands(i)
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val value = if(right==0) -1 else 0
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val value = if(right==0) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSNZ(i: IRInstruction) {
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private fun InsSNZ(i: IRInstruction) {
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val (_: Int, right: Int) = getSetOnConditionOperands(i)
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val (_: Int, right: Int) = getSetOnConditionOperands(i)
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val value = if(right!=0) -1 else 0
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val value = if(right!=0) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSEQ(i: IRInstruction) {
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private fun InsSEQ(i: IRInstruction) {
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val (left: Int, right: Int) = getSetOnConditionOperands(i)
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val (left: Int, right: Int) = getSetOnConditionOperands(i)
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val value = if(left==right) -1 else 0
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val value = if(left==right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSNE(i: IRInstruction) {
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private fun InsSNE(i: IRInstruction) {
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val (left: Int, right: Int) = getSetOnConditionOperands(i)
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val (left: Int, right: Int) = getSetOnConditionOperands(i)
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val value = if(left!=right) -1 else 0
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val value = if(left!=right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSLT(i: IRInstruction) {
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private fun InsSLT(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperandsU(i)
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val (left, right) = getSetOnConditionOperandsU(i)
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val value = if(left<right) -1 else 0
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val value = if(left<right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSLTS(i: IRInstruction) {
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private fun InsSLTS(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperands(i)
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val (left, right) = getSetOnConditionOperands(i)
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val value = if(left<right) -1 else 0
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val value = if(left<right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSGT(i: IRInstruction) {
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private fun InsSGT(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperandsU(i)
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val (left, right) = getSetOnConditionOperandsU(i)
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val value = if(left>right) -1 else 0
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val value = if(left>right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSGTS(i: IRInstruction) {
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private fun InsSGTS(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperands(i)
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val (left, right) = getSetOnConditionOperands(i)
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val value = if(left>right) -1 else 0
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val value = if(left>right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSLE(i: IRInstruction) {
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private fun InsSLE(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperandsU(i)
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val (left, right) = getSetOnConditionOperandsU(i)
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val value = if(left<=right) -1 else 0
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val value = if(left<=right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSLES(i: IRInstruction) {
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private fun InsSLES(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperands(i)
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val (left, right) = getSetOnConditionOperands(i)
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val value = if(left<=right) -1 else 0
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val value = if(left<=right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSGE(i: IRInstruction) {
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private fun InsSGE(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperandsU(i)
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val (left, right) = getSetOnConditionOperandsU(i)
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val value = if(left>=right) -1 else 0
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val value = if(left>=right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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}
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}
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private fun InsSGES(i: IRInstruction) {
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private fun InsSGES(i: IRInstruction) {
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val (left, right) = getSetOnConditionOperands(i)
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val (left, right) = getSetOnConditionOperands(i)
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val value = if(left>=right) -1 else 0
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val value = if(left>=right) 1 else 0
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setResultReg(i.reg1!!, value, i.type!!)
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setResultReg(i.reg1!!, value, i.type!!)
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nextPc()
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nextPc()
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