Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2025-01-10 20:30:23 +00:00
Code Issues Projects Releases Wiki Activity

fix missing opportunities to use TSB instruction

Browse Source
This commit is contained in:
Irmen de Jong 2024-07-24 22:51:49 +02:00
parent d113827753
commit b70ce0015c
3 changed files with 47 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt
View File

@ -715,9 +715,9 @@ private fun optimizeTSBtoRegularOr(linesByFour: Sequence<List<IndexedValue<Strin
val operand2 = second.substring(3) val operand2 = second.substring(3)
val operand3 = third.substring(3) val operand3 = third.substring(3)
if(operand1!=operand2 && operand2==operand3) { if(operand1!=operand2 && operand2==operand3) {
mods.add(Modification(lines[0].index, false, " lda $operand2 ; op2")) mods.add(Modification(lines[0].index, false, " lda $operand2"))
mods.add(Modification(lines[1].index, false, " ora $operand1 ; op1")) mods.add(Modification(lines[1].index, false, " ora $operand1"))
mods.add(Modification(lines[2].index, false, " sta $operand2 ; op2")) mods.add(Modification(lines[2].index, false, " sta $operand2"))
} }
} }
} }

12
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
View File

@ -1088,11 +1088,17 @@ $shortcutLabel:""")
if(asmgen.isTargetCpu(CpuType.CPU65c02)) { if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
if(operator=="&" && value is PtPrefix && value.operator=="~") { if(operator=="&" && value is PtPrefix && value.operator=="~") {
// M &= ~A --> use special TRB 65c02 instruction for that // M &= ~A --> use TRB 65c02 instruction for that
asmgen.assignExpressionToRegister(value.value, RegisterOrPair.A, dt in SignedDatatypes) asmgen.assignExpressionToRegister(value.value, RegisterOrPair.A, dt in SignedDatatypes)
asmgen.out(" trb $name") asmgen.out(" trb $name")
return return
} }
else if(operator=="|") {
// M |= A --> use TSB 65c02 instruction for that
asmgen.assignExpressionToRegister(value, RegisterOrPair.A, dt in SignedDatatypes)
asmgen.out(" tsb $name")
return
}
} }
// normal evaluation // normal evaluation
@ -1106,7 +1112,7 @@ $shortcutLabel:""")
if(asmgen.isTargetCpu(CpuType.CPU65c02)) { if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
if(operator=="|") { if(operator=="|") {
// M |= A --> use special TSB 65c02 instruction for that // M |= A --> use TSB 65c02 instruction for that
asmgen.out(" lda $otherName | tsb $name") asmgen.out(" lda $otherName | tsb $name")
return return
} }
@ -1661,7 +1667,7 @@ $shortcutLabel:""")
} }
private fun immediateOrInplace(name: String, value: Int) { private fun immediateOrInplace(name: String, value: Int) {
if(asmgen.isTargetCpu(CpuType.CPU65c02) && ((value and (value-1))==0)) { if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
asmgen.out(" lda #$value | tsb $name") // set bit asmgen.out(" lda #$value | tsb $name") // set bit
} else { } else {
asmgen.out(" lda $name | ora #$value | sta $name") asmgen.out(" lda $name | ora #$value | sta $name")

140
examples/test.p8
View File

@ -5,114 +5,44 @@
main { main {
sub start() { sub start() {
ubyte @shared variable ubyte @shared v1,v2,v3
v1 = %10011001
v2 = %10101010
v3 = %00111100
variable = 0 v1 &= %00011111
while variable & %10000000 == 0 { v1++
cx16.r0L++ txt.print_ubbin(v1, true)
variable = 128 txt.nl()
}
txt.chrout('1')
while variable & %10000000 != 0 {
cx16.r0L++
variable = 0
}
txt.chrout('2')
while variable & %01000000 == 0 {
cx16.r0L++
variable = 64
}
txt.chrout('3')
while variable & %01000000 != 0 {
cx16.r0L++
variable=0
}
txt.chrout('4')
variable = 255
while variable & %10000000 == 0 {
}
while variable & %01000000 == 0 {
}
txt.chrout('5')
variable = 0
while variable & %10000000 != 0 {
}
while variable & %01000000 != 0 {
}
txt.chrout('6')
txt.chrout('\n')
variable = 0 v1 &= ~v2
cx16.r0L++ v1++
if variable & %10000000 == 0 { txt.print_ubbin(v1, true)
txt.print("bit 7 not set\n") txt.nl()
}
if variable & %10000000 != 0 {
txt.print("bit 7 set\n")
}
if variable & %10000000 == 0 {
txt.print("bit 7 not set\n")
} else {
txt.print("bit 7 set\n")
}
if variable & %10000000 != 0 {
txt.print("bit 7 set\n")
} else {
txt.print("bit 7 not set\n")
}
variable = 128 v1 |= 100
cx16.r0L++ v1++
if variable & %10000000 == 0 { txt.print_ubbin(v1, true)
txt.print("bit 7 not set\n") txt.nl()
}
if variable & %10000000 != 0 {
txt.print("bit 7 set\n")
}
if variable & %10000000 == 0 {
txt.print("bit 7 not set\n")
} else {
txt.print("bit 7 set\n")
}
if variable & %10000000 != 0 {
txt.print("bit 7 set\n")
} else {
txt.print("bit 7 not set\n")
}
if variable & %01000000 == 0 { v1 |= v2
txt.print("bit 6 not set\n") v1++
} txt.print_ubbin(v1, true)
if variable & %01000000 != 0 { txt.nl()
txt.print("bit 6 set\n")
} v1 |= v2 & v3
if variable & %01000000 == 0 { v1++
txt.print("bit 6 not set\n") txt.print_ubbin(v1, true)
} else { txt.nl()
txt.print("bit 6 set\n")
} v1 &= v2|v3
if variable & %01000000 != 0 { v1++
txt.print("bit 6 set\n") txt.print_ubbin(v1, true)
} else { txt.nl()
txt.print("bit 6 not set\n")
} v1 &= ~(v2|v3)
variable = %01000000 v1++
cx16.r0L++ txt.print_ubbin(v1, true)
if variable & %01000000 == 0 { txt.nl()
txt.print("bit 6 not set\n")
}
if variable & %01000000 != 0 {
txt.print("bit 6 set\n")
}
if variable & %01000000 == 0 {
txt.print("bit 6 not set\n")
} else {
txt.print("bit 6 set\n")
}
if variable & %01000000 != 0 {
txt.print("bit 6 set\n")
} else {
txt.print("bit 6 not set\n")
}
} }
} }