mirror of
https://github.com/irmen/prog8.git
synced 2024-06-13 09:29:34 +00:00
IR: handle split arrays without new custom opcodes
This commit is contained in:
Irmen de Jong
parent
0b580ad05d
commit
bfaad1388c
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@ -241,20 +241,24 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(zero) {
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if(fixedIndex!=null) {
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val chunk = IRCodeChunk(null, null).also {
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it += if(targetArray.splitWords)
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IRInstruction(Opcode.STOREZMSPLIT, targetDt, immediate = arrayLength, labelSymbol = "$variable+$fixedIndex")
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if(targetArray.splitWords) {
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_msb+$fixedIndex")
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}
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else
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IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = "$variable+${fixedIndex*itemsize}")
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it += IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = "$variable+${fixedIndex*itemsize}")
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}
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result += chunk
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} else {
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val (code, indexReg) = loadIndexReg(targetArray, itemsize)
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result += code
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result += IRCodeChunk(null, null).also {
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it += if(targetArray.splitWords)
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IRInstruction(Opcode.STOREZXSPLIT, targetDt, reg1 = valueRegister, reg2=indexReg, immediate = arrayLength, labelSymbol = variable)
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if(targetArray.splitWords) {
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it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1 = indexReg, immediate = arrayLength, labelSymbol = variable+"_lsb")
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it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1 = indexReg, immediate = arrayLength, labelSymbol = variable+"_msb")
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}
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else
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IRInstruction(Opcode.STOREZX, targetDt, reg1=indexReg, labelSymbol = variable)
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it += IRInstruction(Opcode.STOREZX, targetDt, reg1=indexReg, labelSymbol = variable)
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}
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}
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} else {
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@ -275,20 +279,28 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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} else {
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if(fixedIndex!=null) {
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val chunk = IRCodeChunk(null, null).also {
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it += if(targetArray.splitWords)
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IRInstruction(Opcode.STOREMSPLIT, targetDt, reg1 = valueRegister, immediate = arrayLength, labelSymbol = "$variable+$fixedIndex")
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if(targetArray.splitWords) {
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val msbReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueRegister, immediate = arrayLength, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = msbReg, reg2 = valueRegister)
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = msbReg, immediate = arrayLength, labelSymbol = "${variable}_msb+$fixedIndex")
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}
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else
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IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = "$variable+${fixedIndex*itemsize}")
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it += IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = "$variable+${fixedIndex*itemsize}")
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}
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result += chunk
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} else {
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val (code, indexReg) = loadIndexReg(targetArray, itemsize)
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result += code
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result += IRCodeChunk(null, null).also {
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it += if(targetArray.splitWords)
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IRInstruction(Opcode.STOREXSPLIT, targetDt, reg1 = valueRegister, reg2=indexReg, immediate = arrayLength, labelSymbol = variable)
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if(targetArray.splitWords) {
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val msbReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = valueRegister, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_lsb")
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it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = msbReg, reg2 = valueRegister)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = msbReg, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_msb")
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}
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else
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IRInstruction(Opcode.STOREX, targetDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable)
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it += IRInstruction(Opcode.STOREX, targetDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable)
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}
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}
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}
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@ -168,11 +168,21 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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resultRegister = codeGen.registers.nextFree()
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if(arrayIx.index is PtNumber) {
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val memOffset = (arrayIx.index as PtNumber).number.toInt()
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addInstr(result, IRInstruction(Opcode.LOADMSPLIT, IRDataType.WORD, reg1=resultRegister, immediate = arrayLength, labelSymbol = "$arrayVarSymbol+$memOffset"), null)
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result += IRCodeChunk(null, null).also {
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val tmpRegMsb = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=resultRegister, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_lsb+$memOffset")
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=tmpRegMsb, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_msb+$memOffset")
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=resultRegister, reg2=tmpRegMsb)
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}
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} else {
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val tr = translateExpression(arrayIx.index)
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addToResult(result, tr, tr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.LOADXSPLIT, IRDataType.WORD, reg1=resultRegister, reg2=tr.resultReg, immediate = arrayLength, labelSymbol = arrayVarSymbol), null)
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result += IRCodeChunk(null, null).also {
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val tmpRegMsb = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=resultRegister, reg2 = tr.resultReg, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_lsb")
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegMsb, reg2 = tr.resultReg, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_msb")
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=resultRegister, reg2=tmpRegMsb)
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}
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}
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return ExpressionCodeResult(result, vmDt, resultRegister, -1)
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}
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@ -457,23 +457,11 @@ class IRCodeGen(
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if(iterableVar.dt==DataType.STR) {
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// iterate over a zero-terminated string
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = indexReg, immediate = 0), null)
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val chunk = IRCodeChunk(loopLabel, null)
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chunk += IRInstruction(
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Opcode.LOADX,
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IRDataType.BYTE,
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reg1 = tmpReg,
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reg2 = indexReg,
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labelSymbol = iterable.name
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)
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chunk += IRInstruction(
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Opcode.BEQ,
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IRDataType.BYTE,
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reg1 = tmpReg,
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immediate = 0,
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labelSymbol = endLabel
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)
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chunk += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = tmpReg, labelSymbol = loopvarSymbol)
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result += chunk
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result += IRCodeChunk(loopLabel, null).also {
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = tmpReg, reg2 = indexReg, labelSymbol = iterable.name)
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it += IRInstruction(Opcode.BEQ, IRDataType.BYTE, reg1 = tmpReg, immediate = 0, labelSymbol = endLabel)
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = tmpReg, labelSymbol = loopvarSymbol)
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}
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result += translateNode(forLoop.statements)
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val jumpChunk = IRCodeChunk(null, null)
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jumpChunk += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1 = indexReg)
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@ -488,8 +476,12 @@ class IRCodeGen(
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val length = iterableVar.length!!
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=indexReg, immediate = 0), null)
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result += IRCodeChunk(loopLabel, null).also {
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it += IRInstruction(Opcode.LOADXSPLIT, irType(elementDt), reg1=tmpReg, reg2=indexReg, immediate = length, labelSymbol=iterable.name)
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it += IRInstruction(Opcode.STOREM, irType(elementDt), reg1=tmpReg, labelSymbol = loopvarSymbol)
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val tmpRegLsb = registers.nextFree()
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val tmpRegMsb = registers.nextFree()
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegLsb, reg2=indexReg, immediate = length, labelSymbol=iterable.name+"_lsb")
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegMsb, reg2=indexReg, immediate = length, labelSymbol=iterable.name+"_msb")
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=tmpRegLsb, reg2=tmpRegMsb)
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it += IRInstruction(Opcode.STOREM, irType(elementDt), reg1=tmpRegLsb, labelSymbol = loopvarSymbol)
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}
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result += translateNode(forLoop.statements)
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result += IRCodeChunk(null, null).also {
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@ -1367,76 +1359,84 @@ class IRCodeGen(
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}
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private fun translate(postIncrDecr: PtPostIncrDecr): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val array = postIncrDecr.target.array
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val operationMem: Opcode
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val operationRegister: Opcode
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val array = postIncrDecr.target.array
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when(postIncrDecr.operator) {
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"++" -> {
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operationMem = if(array?.splitWords==true) Opcode.INCMSPLIT else Opcode.INCM
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operationMem = Opcode.INCM
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operationRegister = Opcode.INC
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}
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"--" -> {
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operationMem = if(array?.splitWords==true) Opcode.DECMSPLIT else Opcode.DECM
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operationMem = Opcode.DECM
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operationRegister = Opcode.DEC
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}
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else -> throw AssemblyError("weird operator")
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}
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val ident = postIncrDecr.target.identifier
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val memory = postIncrDecr.target.memory
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val irDt = irType(postIncrDecr.target.type)
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val result = mutableListOf<IRCodeChunkBase>()
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if(ident!=null) {
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addInstr(result, IRInstruction(operationMem, irDt, labelSymbol = ident.name), null)
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} else if(memory!=null) {
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if(memory.address is PtNumber) {
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val address = (memory.address as PtNumber).number.toInt()
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addInstr(result, IRInstruction(operationMem, irDt, address = address), null)
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if(array?.splitWords==true) {
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val variable = array.variable.name
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val fixedIndex = constIntValue(array.index)
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val iterable = symbolTable.flat.getValue(array.variable.name) as StStaticVariable
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val arrayLength = iterable.length!!
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if(fixedIndex!=null) {
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TODO("split incr decr")
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// addInstr(result, IRInstruction(operationMem, irDt, immediate = arrayLength, labelSymbol="$variable+$fixedIndex"), null)
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} else {
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val tr = expressionEval.translateExpression(memory.address)
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addToResult(result, tr, tr.resultReg, -1)
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val indexTr = expressionEval.translateExpression(array.index)
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addToResult(result, indexTr, indexTr.resultReg, -1)
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val chunk = IRCodeChunk(null, null)
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val incReg = registers.nextFree()
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chunk += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = tr.resultReg)
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chunk += IRInstruction(operationRegister, irDt, reg1 = incReg)
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chunk += IRInstruction(Opcode.STOREI, irDt, reg1 = incReg, reg2 = tr.resultReg)
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TODO("load split")
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// chunk += IRInstruction(Opcode.LOADXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
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// chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
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TODO("store split")
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// chunk += IRInstruction(Opcode.STOREXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
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result += chunk
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}
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} else if (array!=null) {
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val variable = array.variable.name
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val itemsize = program.memsizer.memorySize(array.type)
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val fixedIndex = constIntValue(array.index)
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if(array.splitWords) {
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val iterable = symbolTable.flat.getValue(array.variable.name) as StStaticVariable
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val arrayLength = iterable.length!!
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if(fixedIndex!=null) {
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addInstr(result, IRInstruction(operationMem, irDt, immediate = arrayLength, labelSymbol="$variable+$fixedIndex"), null)
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} else {
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val ident = postIncrDecr.target.identifier
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val memory = postIncrDecr.target.memory
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val irDt = irType(postIncrDecr.target.type)
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if(ident!=null) {
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addInstr(result, IRInstruction(operationMem, irDt, labelSymbol = ident.name), null)
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} else if(memory!=null) {
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if(memory.address is PtNumber) {
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val address = (memory.address as PtNumber).number.toInt()
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addInstr(result, IRInstruction(operationMem, irDt, address = address), null)
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} else {
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val indexTr = expressionEval.translateExpression(array.index)
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addToResult(result, indexTr, indexTr.resultReg, -1)
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val chunk = IRCodeChunk(null, null)
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val incReg = registers.nextFree()
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chunk += IRInstruction(Opcode.LOADXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
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chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
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chunk += IRInstruction(Opcode.STOREXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
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result += chunk
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val tr = expressionEval.translateExpression(memory.address)
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addToResult(result, tr, tr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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val incReg = registers.nextFree()
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it += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = tr.resultReg)
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it += IRInstruction(operationRegister, irDt, reg1 = incReg)
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it += IRInstruction(Opcode.STOREI, irDt, reg1 = incReg, reg2 = tr.resultReg)
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}
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}
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} else {
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} else if (array!=null) {
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val variable = array.variable.name
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val itemsize = program.memsizer.memorySize(array.type)
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val fixedIndex = constIntValue(array.index)
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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addInstr(result, IRInstruction(operationMem, irDt, labelSymbol="$variable+$offset"), null)
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} else {
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val indexTr = expressionEval.translateExpression(array.index)
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addToResult(result, indexTr, indexTr.resultReg, -1)
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val chunk = IRCodeChunk(null, null)
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val incReg = registers.nextFree()
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chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
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chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
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chunk += IRInstruction(Opcode.STOREX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
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result += chunk
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if(itemsize>1)
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result += multiplyByConst(IRDataType.BYTE, indexTr.resultReg, itemsize)
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result += IRCodeChunk(null, null).also {
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val incReg = registers.nextFree()
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it += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
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it += IRInstruction(operationRegister, irDt, reg1=incReg)
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it += IRInstruction(Opcode.STOREX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
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}
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}
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}
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} else
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throw AssemblyError("weird assigntarget")
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} else
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throw AssemblyError("weird assigntarget")
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}
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return result
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}
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@ -1459,10 +1459,10 @@ class IRCodeGen(
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addToResult(result, countTr, countTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.BEQ, irDt, reg1=countTr.resultReg, immediate = 0, labelSymbol = skipRepeatLabel), null)
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result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
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val chunk = IRCodeChunk(null, null)
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chunk += IRInstruction(Opcode.DEC, irDt, reg1=countTr.resultReg)
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chunk += IRInstruction(Opcode.BNE, irDt, reg1=countTr.resultReg, immediate = 0, labelSymbol = repeatLabel)
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result += chunk
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg)
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it += IRInstruction(Opcode.BNE, irDt, reg1 = countTr.resultReg, immediate = 0, labelSymbol = repeatLabel)
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}
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result += IRCodeChunk(skipRepeatLabel, null)
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return result
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}
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@ -697,6 +697,9 @@ internal class AstChecker(private val program: Program,
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}
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}
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}
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if(decl.splitArray && decl.type==VarDeclType.MEMORY)
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err("@split can't be used on memory mapped arrays")
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}
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if(decl.datatype==DataType.STR) {
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@ -1,6 +1,8 @@
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TODO
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====
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- vm: fix the last replacement code for the now removed LOADSPLIT/STORESPLIT opcodes.
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...
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@ -1,30 +1,34 @@
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%import textio
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%option splitarrays
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%zeropage basicsafe
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main {
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sub start() {
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str name1 = "name1"
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str name2 = "name2"
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uword[] names = [name1, name2, "name3"]
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cx16.r0++
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ubyte xx = 2
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names[xx] = "irmen"
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uword ww
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for ww in names {
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txt.print(ww)
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txt.spc()
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}
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txt.nl()
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names = [1111,2222,3333]
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for ww in names {
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txt.print_uw(ww)
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txt.spc()
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}
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txt.nl()
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uword[] names = [name1, name2, "name3"]
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uword ww
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; for ww in names {
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; txt.print(ww)
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; txt.spc()
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; }
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; txt.nl()
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ubyte idx=1
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names[idx] = 2000
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txt.print_uw(names[1])
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names[idx]++
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txt.print_uw(names[1])
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names[idx]--
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txt.print_uw(names[1])
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; names = [1111,2222,3333]
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; for ww in names {
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; txt.print_uw(ww)
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; txt.spc()
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; }
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; txt.nl()
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txt.print("end.")
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repeat {
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}
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}
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}
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@ -185,8 +185,14 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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xml.writeStartElement("VARIABLESNOINIT")
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xml.writeCharacters("\n")
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for (variable in variablesNoInit) {
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val typeStr = getTypeString(variable)
|
||||
xml.writeCharacters("$typeStr ${variable.name} zp=${variable.zpwish}\n")
|
||||
if(variable.dt in SplitWordArrayTypes) {
|
||||
// split into 2 ubyte arrays lsb+msb
|
||||
xml.writeCharacters("ubyte[${variable.length}] ${variable.name}_lsb zp=${variable.zpwish}\n")
|
||||
xml.writeCharacters("ubyte[${variable.length}] ${variable.name}_msb zp=${variable.zpwish}\n")
|
||||
} else {
|
||||
val typeStr = getTypeString(variable)
|
||||
xml.writeCharacters("$typeStr ${variable.name} zp=${variable.zpwish}\n")
|
||||
}
|
||||
}
|
||||
|
||||
xml.writeEndElement()
|
||||
|
|
@ -195,36 +201,60 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
|
|||
xml.writeCharacters("\n")
|
||||
|
||||
for (variable in variablesWithInit) {
|
||||
val typeStr = getTypeString(variable)
|
||||
val value: String = when(variable.dt) {
|
||||
DataType.FLOAT -> (variable.onetimeInitializationNumericValue ?: "").toString()
|
||||
in NumericDatatypes -> (variable.onetimeInitializationNumericValue?.toInt()?.toHex() ?: "").toString()
|
||||
DataType.STR -> {
|
||||
val encoded = irProgram.encoding.encodeString(variable.onetimeInitializationStringValue!!.first, variable.onetimeInitializationStringValue!!.second) + listOf(0u)
|
||||
encoded.joinToString(",") { it.toInt().toString() }
|
||||
}
|
||||
DataType.ARRAY_F -> {
|
||||
if(variable.onetimeInitializationArrayValue!=null) {
|
||||
variable.onetimeInitializationArrayValue!!.joinToString(",") { it.number!!.toString() }
|
||||
} else {
|
||||
"" // array will be zero'd out at program start
|
||||
if(variable.dt in SplitWordArrayTypes) {
|
||||
val lsbValue: String
|
||||
val msbValue: String
|
||||
if(variable.onetimeInitializationArrayValue==null) {
|
||||
lsbValue = ""
|
||||
msbValue = ""
|
||||
} else {
|
||||
lsbValue = variable.onetimeInitializationArrayValue!!.joinToString(",") {
|
||||
if(it.number!=null)
|
||||
(it.number!!.toInt() and 255).toHex()
|
||||
else
|
||||
"@<${it.addressOfSymbol}"
|
||||
}
|
||||
msbValue = variable.onetimeInitializationArrayValue!!.joinToString(",") {
|
||||
if(it.number!=null)
|
||||
(it.number!!.toInt() shr 8).toHex()
|
||||
else
|
||||
"@>${it.addressOfSymbol}"
|
||||
}
|
||||
}
|
||||
in ArrayDatatypes -> {
|
||||
if(variable.onetimeInitializationArrayValue!==null) {
|
||||
variable.onetimeInitializationArrayValue!!.joinToString(",") {
|
||||
if(it.number!=null)
|
||||
it.number!!.toInt().toHex()
|
||||
else
|
||||
"@${it.addressOfSymbol}"
|
||||
xml.writeCharacters("ubyte[${variable.length}] ${variable.name}_lsb=$lsbValue zp=${variable.zpwish}\n")
|
||||
xml.writeCharacters("ubyte[${variable.length}] ${variable.name}_msb=$msbValue zp=${variable.zpwish}\n")
|
||||
} else {
|
||||
val typeStr = getTypeString(variable)
|
||||
val value: String = when(variable.dt) {
|
||||
DataType.FLOAT -> (variable.onetimeInitializationNumericValue ?: "").toString()
|
||||
in NumericDatatypes -> (variable.onetimeInitializationNumericValue?.toInt()?.toHex() ?: "").toString()
|
||||
DataType.STR -> {
|
||||
val encoded = irProgram.encoding.encodeString(variable.onetimeInitializationStringValue!!.first, variable.onetimeInitializationStringValue!!.second) + listOf(0u)
|
||||
encoded.joinToString(",") { it.toInt().toString() }
|
||||
}
|
||||
DataType.ARRAY_F -> {
|
||||
if(variable.onetimeInitializationArrayValue!=null) {
|
||||
variable.onetimeInitializationArrayValue!!.joinToString(",") { it.number!!.toString() }
|
||||
} else {
|
||||
"" // array will be zero'd out at program start
|
||||
}
|
||||
} else {
|
||||
"" // array will be zero'd out at program start
|
||||
}
|
||||
in ArrayDatatypes -> {
|
||||
if(variable.onetimeInitializationArrayValue!==null) {
|
||||
variable.onetimeInitializationArrayValue!!.joinToString(",") {
|
||||
if(it.number!=null)
|
||||
it.number!!.toInt().toHex()
|
||||
else
|
||||
"@${it.addressOfSymbol}"
|
||||
}
|
||||
} else {
|
||||
"" // array will be zero'd out at program start
|
||||
}
|
||||
}
|
||||
else -> throw InternalCompilerException("weird dt")
|
||||
}
|
||||
else -> throw InternalCompilerException("weird dt")
|
||||
xml.writeCharacters("$typeStr ${variable.name}=$value zp=${variable.zpwish}\n")
|
||||
}
|
||||
xml.writeCharacters("$typeStr ${variable.name}=$value zp=${variable.zpwish}\n")
|
||||
}
|
||||
xml.writeEndElement()
|
||||
xml.writeCharacters("\n")
|
||||
|
|
|
|||
|
|
@ -36,15 +36,11 @@ load reg1, value - load immediate value into register. If y
|
|||
loadm reg1, address - load reg1 with value at memory address
|
||||
loadi reg1, reg2 - load reg1 with value at memory indirect, memory pointed to by reg2
|
||||
loadx reg1, reg2, address - load reg1 with value at memory address indexed by value in reg2
|
||||
loadxsplit reg1, reg2, arraylength, arrayaddress - load reg1 word with value from "split lsb/msb array" indexed by reg2
|
||||
loadmsplit reg1, arraylength, indexedarrayaddress - load reg1 word with value from "split lsb/msb array" element at indexedarrayaddress
|
||||
loadix reg1, reg2, pointeraddr - load reg1 with value at memory indirect, pointed to by pointeraddr indexed by value in reg2
|
||||
loadr reg1, reg2 - load reg1 with value in register reg2
|
||||
storem reg1, address - store reg1 at memory address
|
||||
storei reg1, reg2 - store reg1 at memory indirect, memory pointed to by reg2
|
||||
storex reg1, reg2, address - store reg1 at memory address, indexed by value in reg2
|
||||
storexsplit reg1, reg2, arraylength, arrayaddress - store reg1 word in "split lsb/msb array", indexed by value in reg2
|
||||
storemsplit reg1, arraylength, indexedarrayaddress - store reg1 word in "split lsb/msb array" element at indexedarrayaddress
|
||||
storeix reg1, reg2, pointeraddr - store reg1 at memory indirect, pointed to by pointeraddr indexed by value in reg2
|
||||
storezm address - store zero at memory address
|
||||
storezi reg1 - store zero at memory pointed to by reg1
|
||||
|
|
@ -121,10 +117,8 @@ exts reg1 - reg1 = signed extension of reg1 (b
|
|||
ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (ext.w not yet implemented as we don't have longs yet)
|
||||
inc reg1 - reg1 = reg1+1
|
||||
incm address - memory at address += 1
|
||||
incmsplit arraylen, address - memory at address += 1 (in lsb/msb split word array)
|
||||
dec reg1 - reg1 = reg1-1
|
||||
decm address - memory at address -= 1
|
||||
decmsplit arraylen, address - memory at address -= 1 (in lsb/msb split word array)
|
||||
neg reg1 - reg1 = sign negation of reg1
|
||||
negm address - sign negate memory at address
|
||||
addr reg1, reg2 - reg1 += reg2
|
||||
|
|
@ -233,21 +227,15 @@ enum class Opcode {
|
|||
LOADM,
|
||||
LOADI,
|
||||
LOADX,
|
||||
LOADXSPLIT,
|
||||
LOADMSPLIT,
|
||||
LOADIX,
|
||||
LOADR,
|
||||
STOREM,
|
||||
STOREI,
|
||||
STOREX,
|
||||
STOREXSPLIT,
|
||||
STOREMSPLIT,
|
||||
STOREIX,
|
||||
STOREZM,
|
||||
STOREZI,
|
||||
STOREZX,
|
||||
STOREZXSPLIT,
|
||||
STOREZMSPLIT,
|
||||
|
||||
JUMP,
|
||||
JUMPA,
|
||||
|
|
@ -295,10 +283,8 @@ enum class Opcode {
|
|||
|
||||
INC,
|
||||
INCM,
|
||||
INCMSPLIT,
|
||||
DEC,
|
||||
DECM,
|
||||
DECMSPLIT,
|
||||
NEG,
|
||||
NEGM,
|
||||
ADDR,
|
||||
|
|
@ -516,21 +502,15 @@ val instructionFormats = mutableMapOf(
|
|||
Opcode.LOADM to InstructionFormat.from("BW,>r1,<a | F,>fr1,<a"),
|
||||
Opcode.LOADI to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<r1"),
|
||||
Opcode.LOADX to InstructionFormat.from("BW,>r1,<r2,<a | F,>fr1,<r1,<a"),
|
||||
Opcode.LOADXSPLIT to InstructionFormat.from("W,>r1,<r2,<i,<a"),
|
||||
Opcode.LOADMSPLIT to InstructionFormat.from("W,>r1,<i,<a"),
|
||||
Opcode.LOADIX to InstructionFormat.from("BW,>r1,<r2,<a | F,>fr1,<r1,<a"),
|
||||
Opcode.LOADR to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<fr2"),
|
||||
Opcode.STOREM to InstructionFormat.from("BW,<r1,>a | F,<fr1,>a"),
|
||||
Opcode.STOREI to InstructionFormat.from("BW,<r1,<r2 | F,<fr1,<r1"),
|
||||
Opcode.STOREX to InstructionFormat.from("BW,<r1,<r2,>a | F,<fr1,<r1,>a"),
|
||||
Opcode.STOREXSPLIT to InstructionFormat.from("W,<r1,<r2,<i,>a"),
|
||||
Opcode.STOREMSPLIT to InstructionFormat.from("W,<r1,<i,>a"),
|
||||
Opcode.STOREIX to InstructionFormat.from("BW,<r1,<r2,>a | F,<fr1,<r1,>a"),
|
||||
Opcode.STOREZM to InstructionFormat.from("BW,>a | F,>a"),
|
||||
Opcode.STOREZI to InstructionFormat.from("BW,<r1 | F,<r1"),
|
||||
Opcode.STOREZX to InstructionFormat.from("BW,<r1,>a | F,<r1,>a"),
|
||||
Opcode.STOREZMSPLIT to InstructionFormat.from("W,<i,>a"),
|
||||
Opcode.STOREZXSPLIT to InstructionFormat.from("W,<r1,<i,>a"),
|
||||
Opcode.JUMP to InstructionFormat.from("N,<a"),
|
||||
Opcode.JUMPA to InstructionFormat.from("N,<a"),
|
||||
Opcode.CALL to InstructionFormat.from("N,call"),
|
||||
|
|
@ -575,10 +555,8 @@ val instructionFormats = mutableMapOf(
|
|||
Opcode.SGES to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.INC to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.INCM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.INCMSPLIT to InstructionFormat.from("W,<i,<>a"),
|
||||
Opcode.DEC to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.DECM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.DECMSPLIT to InstructionFormat.from("W,<i,<>a"),
|
||||
Opcode.NEG to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.NEGM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.ADDR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
|
|
|
|||
|
|
@ -14,10 +14,9 @@ fun getTypeString(dt : DataType): String = when(dt) {
|
|||
DataType.ARRAY_UB, DataType.STR -> "ubyte[]"
|
||||
DataType.ARRAY_B -> "byte[]"
|
||||
DataType.ARRAY_UW -> "uword[]"
|
||||
DataType.ARRAY_UW_SPLIT -> "uword_split[]"
|
||||
DataType.ARRAY_W -> "word[]"
|
||||
DataType.ARRAY_W_SPLIT -> "word_split[]"
|
||||
DataType.ARRAY_F -> "float[]"
|
||||
in SplitWordArrayTypes -> throw InternalCompilerException("split array should have been converted to 2 ubyte arrays")
|
||||
else -> throw InternalCompilerException("weird dt")
|
||||
}
|
||||
|
||||
|
|
@ -31,10 +30,9 @@ fun getTypeString(memvar: StMemVar): String = when(memvar.dt) {
|
|||
DataType.ARRAY_UB, DataType.STR -> "ubyte[${memvar.length}]"
|
||||
DataType.ARRAY_B -> "byte[${memvar.length}]"
|
||||
DataType.ARRAY_UW -> "uword[${memvar.length}]"
|
||||
DataType.ARRAY_UW_SPLIT -> "uword_split[${memvar.length}]"
|
||||
DataType.ARRAY_W -> "word[${memvar.length}]"
|
||||
DataType.ARRAY_W_SPLIT -> "word_split[${memvar.length}]"
|
||||
DataType.ARRAY_F -> "float[${memvar.length}]"
|
||||
in SplitWordArrayTypes -> throw InternalCompilerException("@split can't be used on memory mapped arrays")
|
||||
else -> throw InternalCompilerException("weird dt")
|
||||
}
|
||||
|
||||
|
|
@ -48,10 +46,9 @@ fun getTypeString(variable : StStaticVariable): String = when(variable.dt) {
|
|||
DataType.ARRAY_UB, DataType.STR -> "ubyte[${variable.length}]"
|
||||
DataType.ARRAY_B -> "byte[${variable.length}]"
|
||||
DataType.ARRAY_UW -> "uword[${variable.length}]"
|
||||
DataType.ARRAY_UW_SPLIT -> "uword_split[${variable.length}]"
|
||||
DataType.ARRAY_W -> "word[${variable.length}]"
|
||||
DataType.ARRAY_W_SPLIT -> "word_split[${variable.length}]"
|
||||
DataType.ARRAY_F -> "float[${variable.length}]"
|
||||
in SplitWordArrayTypes -> throw InternalCompilerException("split array should have been converted to 2 ubyte arrays")
|
||||
else -> throw InternalCompilerException("weird dt")
|
||||
}
|
||||
|
||||
|
|
@ -78,6 +75,8 @@ fun parseIRValue(value: String): Float {
|
|||
throw IRParseException("attempt to parse a label as numeric value")
|
||||
else if(value.startsWith('&'))
|
||||
throw IRParseException("address-of should be done with normal LOAD <symbol>")
|
||||
else if(value.startsWith('@'))
|
||||
throw IRParseException("address-of @ should have been handled earlier")
|
||||
else
|
||||
return value.toFloat()
|
||||
}
|
||||
|
|
|
|||
|
|
@ -164,17 +164,11 @@ class VirtualMachine(irProgram: IRProgram) {
|
|||
Opcode.LOAD -> InsLOAD(ins)
|
||||
Opcode.LOADM -> InsLOADM(ins)
|
||||
Opcode.LOADX -> InsLOADX(ins)
|
||||
Opcode.LOADXSPLIT -> InsLOADXSPLIT(ins)
|
||||
Opcode.LOADMSPLIT -> InsLOADMSPLIT(ins)
|
||||
Opcode.LOADI -> InsLOADI(ins)
|
||||
Opcode.LOADIX -> InsLOADIX(ins)
|
||||
Opcode.LOADR -> InsLOADR(ins)
|
||||
Opcode.STOREM -> InsSTOREM(ins)
|
||||
Opcode.STOREX -> InsSTOREX(ins)
|
||||
Opcode.STOREXSPLIT -> InsSTOREXSPLIT(ins)
|
||||
Opcode.STOREZXSPLIT -> InsSTOREZXSPLIT(ins)
|
||||
Opcode.STOREMSPLIT -> InsSTOREMSPLIT(ins)
|
||||
Opcode.STOREZMSPLIT -> InsSTOREZMSPLIT(ins)
|
||||
Opcode.STOREIX -> InsSTOREIX(ins)
|
||||
Opcode.STOREI -> InsSTOREI(ins)
|
||||
Opcode.STOREZM -> InsSTOREZM(ins)
|
||||
|
|
@ -223,10 +217,8 @@ class VirtualMachine(irProgram: IRProgram) {
|
|||
Opcode.SGES -> InsSGES(ins)
|
||||
Opcode.INC -> InsINC(ins)
|
||||
Opcode.INCM -> InsINCM(ins)
|
||||
Opcode.INCMSPLIT -> InsINCMSPLIT(ins)
|
||||
Opcode.DEC -> InsDEC(ins)
|
||||
Opcode.DECM -> InsDECM(ins)
|
||||
Opcode.DECMSPLIT -> InsDECMSPLIT(ins)
|
||||
Opcode.NEG -> InsNEG(ins)
|
||||
Opcode.NEGM -> InsNEGM(ins)
|
||||
Opcode.ADDR -> InsADDR(ins)
|
||||
|
|
@ -421,60 +413,6 @@ class VirtualMachine(irProgram: IRProgram) {
|
|||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsLOADXSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!! + registers.getUW(i.reg2!!).toInt()
|
||||
val lsb = memory.getUB(address)
|
||||
val msb = memory.getUB(address+i.immediate!!)
|
||||
registers.setUW(i.reg1!!, ((msb.toInt() shl 8) or lsb.toInt()).toUShort())
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsLOADMSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!!
|
||||
val lsb = memory.getUB(address)
|
||||
val msb = memory.getUB(address+i.immediate!!)
|
||||
registers.setUW(i.reg1!!, ((msb.toInt() shl 8) or lsb.toInt()).toUShort())
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsSTOREXSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!! + registers.getUW(i.reg2!!).toInt()
|
||||
val lsb = registers.getUW(i.reg1!!).toUByte()
|
||||
val msb = (registers.getUW(i.reg1!!).toInt() shr 8).toUByte()
|
||||
memory.setUB(address, lsb)
|
||||
memory.setUB(address+i.immediate!!, msb)
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsSTOREMSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!!
|
||||
val lsb = registers.getUW(i.reg1!!).toUByte()
|
||||
val msb = (registers.getUW(i.reg1!!).toInt() shr 8).toUByte()
|
||||
memory.setUB(address, lsb)
|
||||
memory.setUB(address+i.immediate!!, msb)
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsSTOREZXSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!! + registers.getUW(i.reg2!!).toInt()
|
||||
memory.setUB(address, 0u)
|
||||
memory.setUB(address+i.immediate!!, 0u)
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsSTOREZMSPLIT(i: IRInstruction) {
|
||||
require(i.type==IRDataType.WORD)
|
||||
val address = i.address!!
|
||||
memory.setUB(address, 0u)
|
||||
memory.setUB(address+i.immediate!!, 0u)
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsLOADIX(i: IRInstruction) {
|
||||
when (i.type!!) {
|
||||
IRDataType.BYTE -> {
|
||||
|
|
@ -921,20 +859,6 @@ class VirtualMachine(irProgram: IRProgram) {
|
|||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsINCMSPLIT(i: IRInstruction) {
|
||||
val address = i.address!!
|
||||
var lsb = memory.getUB(address).toInt()
|
||||
var msb = memory.getUB(address+i.immediate!!).toInt()
|
||||
lsb++
|
||||
if(lsb>255) {
|
||||
lsb = 0
|
||||
msb++
|
||||
}
|
||||
memory.setUB(address, lsb.toUByte())
|
||||
memory.setUB(address+i.immediate!!, msb.toUByte())
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsDEC(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1!!)-1u).toUByte())
|
||||
|
|
@ -953,21 +877,6 @@ class VirtualMachine(irProgram: IRProgram) {
|
|||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsDECMSPLIT(i: IRInstruction) {
|
||||
val address = i.address!!
|
||||
var lsb = memory.getUB(address).toInt()
|
||||
var msb = memory.getUB(address+i.immediate!!).toInt()
|
||||
lsb--
|
||||
if(lsb<0) {
|
||||
lsb = 255
|
||||
msb--
|
||||
}
|
||||
memory.setUB(address, lsb.toUByte())
|
||||
memory.setUB(address+i.immediate!!, msb.toUByte())
|
||||
nextPc()
|
||||
|
||||
}
|
||||
|
||||
private fun InsNEG(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1!!).toInt()).toUByte())
|
||||
|
|
|
|||
|
|
@ -295,7 +295,20 @@ class VmProgramLoader {
|
|||
when(variable.dt) {
|
||||
DataType.STR, DataType.ARRAY_UB -> {
|
||||
for(elt in it) {
|
||||
memory.setUB(addr, elt.number!!.toInt().toUByte())
|
||||
if(elt.addressOfSymbol!=null) {
|
||||
val name = elt.addressOfSymbol!!
|
||||
val symbolAddress = if(name.startsWith('<')) {
|
||||
symbolAddresses[name.drop(1)]?.and(255)
|
||||
?: throw IRParseException("vm cannot yet load a label address as a value: $name") // TODO
|
||||
} else if(name.startsWith('>')) {
|
||||
symbolAddresses[name.drop(1)]?.shr(8)
|
||||
?: throw IRParseException("vm cannot yet load a label address as a value: $name") // TODO
|
||||
} else
|
||||
throw IRParseException("for byte-array address-of, expected < or > (lsb/msb)")
|
||||
memory.setUB(addr, symbolAddress.toUByte())
|
||||
} else {
|
||||
memory.setUB(addr, elt.number!!.toInt().toUByte())
|
||||
}
|
||||
addr++
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user