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https://github.com/irmen/prog8.git
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R0-R15 register parameter optimization if loaded with byte instead of word
This commit is contained in:
Irmen de Jong
parent
6734ae3c88
commit
c2a8dc23d0
@ -9,6 +9,8 @@ import prog8.ast.statements.RegisterOrStatusflag
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import prog8.ast.statements.Subroutine
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import prog8.ast.statements.SubroutineParameter
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import prog8.compiler.AssemblyError
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import prog8.compiler.target.CompilationTarget
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import prog8.compiler.target.CpuType
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import prog8.compiler.target.c64.codegen.assignment.*
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@ -96,6 +98,7 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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asmgen.out(" inx") // align estack pointer
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for(argi in stmt.args.zip(sub.asmParameterRegisters).withIndex()) {
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val plusIdxStr = if(argi.index==0) "" else "+${argi.index}"
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when {
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argi.value.second.statusflag == Statusflag.Pc -> {
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require(argForCarry == null)
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@ -111,24 +114,40 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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argForAregister = argi
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}
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argi.value.second.registerOrPair == RegisterOrPair.Y -> {
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asmgen.out(" ldy P8ESTACK_LO+${argi.index},x")
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asmgen.out(" ldy P8ESTACK_LO$plusIdxStr,x")
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}
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argi.value.second.registerOrPair in Cx16VirtualRegisters -> {
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// immediately output code to load the virtual register, to avoid clobbering the A register later
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asmgen.out("""
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lda P8ESTACK_LO+${argi.index},x
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}
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lda P8ESTACK_HI+${argi.index},x
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}+1
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""")
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// immediately output code to load the virtual register, to avoid clobbering the A register later
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when (sub.parameters[argi.index].type) {
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in ByteDatatypes -> {
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// only load the lsb of the virtual register
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asmgen.out("""
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lda P8ESTACK_LO$plusIdxStr,x
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}
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""")
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if (CompilationTarget.instance.machine.cpu == CpuType.CPU65c02)
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asmgen.out(" stz cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}+1")
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else
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asmgen.out(" lda #0 | sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}+1")
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}
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in WordDatatypes ->
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asmgen.out("""
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lda P8ESTACK_LO$plusIdxStr,x
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}
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lda P8ESTACK_HI$plusIdxStr,x
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sta cx16.${argi.value.second.registerOrPair.toString().toLowerCase()}+1
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""")
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else -> throw AssemblyError("weird dt")
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}
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}
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else -> throw AssemblyError("weird argument")
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}
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}
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if(argForCarry!=null) {
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val plusIdxStr = if(argForCarry.index==0) "" else "+${argForCarry.index}"
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asmgen.out("""
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lda P8ESTACK_LO+${argForCarry.index},x
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lda P8ESTACK_LO$plusIdxStr,x
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beq +
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sec
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bcs ++
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@ -137,21 +156,23 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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}
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if(argForAregister!=null) {
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val plusIdxStr = if(argForAregister.index==0) "" else "+${argForAregister.index}"
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when(argForAregister.value.second.registerOrPair) {
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RegisterOrPair.A -> asmgen.out(" lda P8ESTACK_LO+${argForAregister.index},x")
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RegisterOrPair.AY -> asmgen.out(" lda P8ESTACK_LO+${argForAregister.index},x | ldy P8ESTACK_HI+${argForAregister.index},x")
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RegisterOrPair.A -> asmgen.out(" lda P8ESTACK_LO$plusIdxStr,x")
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RegisterOrPair.AY -> asmgen.out(" lda P8ESTACK_LO$plusIdxStr,x | ldy P8ESTACK_HI$plusIdxStr,x")
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else -> throw AssemblyError("weird arg")
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}
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}
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if(argForXregister!=null) {
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val plusIdxStr = if(argForXregister.index==0) "" else "+${argForXregister.index}"
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if(argForAregister!=null)
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asmgen.out(" pha")
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when(argForXregister.value.second.registerOrPair) {
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RegisterOrPair.X -> asmgen.out(" lda P8ESTACK_LO+${argForXregister.index},x | tax")
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RegisterOrPair.AX -> asmgen.out(" ldy P8ESTACK_LO+${argForXregister.index},x | lda P8ESTACK_HI+${argForXregister.index},x | tax | tya")
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RegisterOrPair.XY -> asmgen.out(" ldy P8ESTACK_HI+${argForXregister.index},x | lda P8ESTACK_LO+${argForXregister.index},x | tax")
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RegisterOrPair.X -> asmgen.out(" lda P8ESTACK_LO$plusIdxStr,x | tax")
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RegisterOrPair.AX -> asmgen.out(" ldy P8ESTACK_LO$plusIdxStr,x | lda P8ESTACK_HI$plusIdxStr,x | tax | tya")
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RegisterOrPair.XY -> asmgen.out(" ldy P8ESTACK_HI$plusIdxStr,x | lda P8ESTACK_LO$plusIdxStr,x | tax")
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else -> throw AssemblyError("weird arg")
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}
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if(argForAregister!=null)
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@ -242,7 +263,11 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
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asmgen.assignVariableToRegister(scratchVar, register)
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}
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else {
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val target = AsmAssignTarget.fromRegisters(register, sub, program, asmgen)
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val target: AsmAssignTarget =
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if(parameter.value.type in ByteDatatypes && (register==RegisterOrPair.AX || register == RegisterOrPair.AY || register==RegisterOrPair.XY || register in Cx16VirtualRegisters))
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AsmAssignTarget(TargetStorageKind.REGISTER, program, asmgen, parameter.value.type, sub, register = register)
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else
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AsmAssignTarget.fromRegisters(register, sub, program, asmgen)
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val src = if(valueDt in PassByReferenceDatatypes) {
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if(value is IdentifierReference) {
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val addr = AddressOf(value, Position.DUMMY)
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@ -1559,12 +1559,11 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.XY -> asmgen.out(" ldx #${byte.toHex()} | ldy #0")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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lda #${byte.toHex()}
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sta cx16.${target.register.toString().toLowerCase()}
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lda #0
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sta cx16.${target.register.toString().toLowerCase()}+1
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""")
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asmgen.out(" lda #${byte.toHex()} | sta cx16.${target.register.toString().toLowerCase()}")
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if(CompilationTarget.instance.machine.cpu == CpuType.CPU65c02)
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asmgen.out(" stz cx16.${target.register.toString().toLowerCase()}+1\n")
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else
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asmgen.out(" lda #0 | sta cx16.${target.register.toString().toLowerCase()}+1\n")
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}
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else -> throw AssemblyError("weird register")
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}
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@ -1,34 +1,10 @@
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%import textio
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%import diskio
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%import floats
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%import graphics
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%import test_stack
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%zeropage basicsafe
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%option no_sysinit
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main {
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; TODO the R0 is loaded as a WORD even though its type is specified as a BYTE...:
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asmsub set_8_pixels_from_bits(ubyte bits @R0, ubyte oncolor @A, ubyte offcolor @Y) {
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}
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asmsub derp(ubyte value @A, uword address @R0) {
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%asm {{
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rts
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}}
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}
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sub start () {
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uword bank = 1
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uword address = 1000
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ubyte value = 123
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bank++
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derp(value, address)
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cx16.vpoke(lsb(bank), address, value)
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test_stack.test()
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}
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