get rid of certain redundant !=0 comparisons in logical expressions

This commit is contained in:
Irmen de Jong 2024-02-01 21:50:01 +01:00
parent 9f8e61789a
commit c71aa0895f
2 changed files with 21 additions and 4 deletions

View File

@ -151,6 +151,27 @@ internal class VariousCleanups(val program: Program, val errors: IErrorReporter,
} }
} }
} }
if(expr.operator in LogicalOperators) {
// remove redundant !=0 comparisons from logical expressions such as: a!=0 xor b --> a xor b (only for byte operands!)
val leftExpr = expr.left as? BinaryExpression
if(leftExpr != null &&
leftExpr.operator == "!=" &&
!leftExpr.left.isSimple &&
leftExpr.left.inferType(program).isBytes &&
leftExpr.right.constValue(program)?.number == 0.0) {
return listOf(IAstModification.ReplaceNode(leftExpr, leftExpr.left, expr))
}
val rightExpr = expr.right as? BinaryExpression
if(rightExpr != null &&
rightExpr.operator == "!=" &&
!rightExpr.left.isSimple &&
rightExpr.left.inferType(program).isBytes &&
rightExpr.right.constValue(program)?.number == 0.0) {
return listOf(IAstModification.ReplaceNode(rightExpr, rightExpr.left, expr))
}
}
return noModifications return noModifications
} }

View File

@ -1,10 +1,6 @@
TODO TODO
==== ====
maze: if cell & UP!=0 and @(celladdr(cx,cy-1)) & (WALKED|BACKTRACKED) ==0
^^ adding this !=0 caused a weird beq + / lda #1 / + to appear in front of the shortcircuit beq...
(after merge in boolean): move all "OperatorXinplace" from expressionGen to AssignmentGen, see if we can get rid of the Result return type. (after merge in boolean): move all "OperatorXinplace" from expressionGen to AssignmentGen, see if we can get rid of the Result return type.
... ...