Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2024-10-07 00:55:33 +00:00
Code Issues Projects Releases Wiki Activity

gfx2 optimizations for vertical lines

Browse Source
This commit is contained in:
Irmen de Jong 2020-12-29 02:13:38 +01:00
parent f80e462d25
commit c81952c356
2 changed files with 82 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
compiler/res/prog8lib/cx16/gfx2.p8
View File

@ -211,8 +211,8 @@ _done
} }
sub vertical_line(uword x, uword y, uword height, ubyte color) { sub vertical_line(uword x, uword y, uword height, ubyte color) {
position(x,y)
if active_mode==1 { if active_mode==1 {
position(x,y)
; set vera auto-increment to 320 pixel increment (=next line) ; set vera auto-increment to 320 pixel increment (=next line)
cx16.VERA_ADDR_H = (cx16.VERA_ADDR_H & %00000111) | (14<<4) cx16.VERA_ADDR_H = (cx16.VERA_ADDR_H & %00000111) | (14<<4)
%asm {{ %asm {{
@ -226,10 +226,81 @@ _done
} }
; note for the 1 bpp modes we can't use vera's auto increment mode because we have to 'or' the pixel data in place. ; note for the 1 bpp modes we can't use vera's auto increment mode because we have to 'or' the pixel data in place.
; TODO optimize by manually advancing the vera's data pointer (note stipple and black color!) cx16.VERA_ADDR_H = (cx16.VERA_ADDR_H & %00000111) ; no auto advance
repeat height { cx16.r15 = gfx2.plot.bits[x as ubyte & 7] ; bitmask
plot(x, y, color) if color {
y++ if monochrome_dont_stipple_flag {
repeat height {
%asm {{
lda cx16.VERA_DATA0
ora cx16.r15
sta cx16.VERA_DATA0
lda cx16.VERA_ADDR_L
clc
adc #640/8 ; advance vera data ptr to go to the next line
sta cx16.VERA_ADDR_L
lda cx16.VERA_ADDR_M
adc #0
sta cx16.VERA_ADDR_M
; lda cx16.VERA_ADDR_H ; the bitmap size is small enough to not have to deal with the _H part.
; adc #0
; sta cx16.VERA_ADDR_H
}}
}
} else {
; stippling
%asm {{
lda x
eor y
and #1
bne +
lda cx16.VERA_ADDR_L
clc
adc #<640/8*1 ; advance vera data ptr to go to the next line, for correct stipple pattern
sta cx16.VERA_ADDR_L
lda cx16.VERA_ADDR_M
adc #0
sta cx16.VERA_ADDR_M
+
lsr height+1
ror height
ldy height
- lda cx16.VERA_DATA0
ora cx16.r15
sta cx16.VERA_DATA0
lda cx16.VERA_ADDR_L
clc
adc #<640/8*2 ; advance vera data ptr to go to the next-next line
sta cx16.VERA_ADDR_L
lda cx16.VERA_ADDR_M
adc #0
sta cx16.VERA_ADDR_M
; lda cx16.VERA_ADDR_H ; the bitmap size is small enough to not have to deal with the _H part.
; adc #0
; sta cx16.VERA_ADDR_H
dey
bne -
}}
}
} else {
cx16.r15 = ~cx16.r15
repeat height {
%asm {{
lda cx16.VERA_DATA0
and cx16.r15
sta cx16.VERA_DATA0
lda cx16.VERA_ADDR_L
clc
adc #640/8 ; advance vera data ptr to go to the next line
sta cx16.VERA_ADDR_L
lda cx16.VERA_ADDR_M
adc #0
sta cx16.VERA_ADDR_M
; lda cx16.VERA_ADDR_H ; the bitmap size is small enough to not have to deal with the _H part.
; adc #0
; sta cx16.VERA_ADDR_H
}}
}
} }
} }

6
examples/cx16/testgfx2.p8
View File

@ -16,9 +16,15 @@ main {
uword cnt uword cnt
pp=pixels pp=pixels
gfx2.monochrome_stipple(true)
gfx2.disc(320,240,200,1)
for xx in 0 to 639 { for xx in 0 to 639 {
gfx2.vertical_line(xx, 0, 480, 1) gfx2.vertical_line(xx, 0, 480, 1)
} }
for xx in 0 to 639 {
gfx2.vertical_line(xx, 0, 480, 0)
}
cx16.wait(200)
gfx2.screen_mode(255) gfx2.screen_mode(255)
txt.print("done!\n") txt.print("done!\n")
return return