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https://github.com/irmen/prog8.git
synced 2024-06-10 20:29:33 +00:00
vm: remove BNE opcode -> CMPI + BSTNE
This commit is contained in:
Irmen de Jong
parent
eb64d92333
commit
cdf5a8f20f
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@ -565,12 +565,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1)
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg)
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if (notEquals) {
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it += IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=valueReg, immediate = 0, labelSymbol = label)
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} else {
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0)
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = label)
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}
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0)
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it += if (notEquals)
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IRInstruction(Opcode.BSTNE, labelSymbol = label)
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else
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IRInstruction(Opcode.BSTEQ, labelSymbol = label)
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0)
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}
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result += IRCodeChunk(label, null)
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@ -499,7 +499,8 @@ class IRCodeGen(
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result += translateNode(forLoop.statements)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexReg)
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it += IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=indexReg, immediate = if(iterableLength==256) 0 else iterableLength, labelSymbol = loopLabel)
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=indexReg, immediate = if(iterableLength==256) 0 else iterableLength)
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it += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel)
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}
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}
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else -> {
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@ -514,7 +515,10 @@ class IRCodeGen(
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}
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result += translateNode(forLoop.statements)
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result += addConstReg(IRDataType.BYTE, indexReg, elementSize)
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addInstr(result, IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=indexReg, immediate = if(lengthBytes==256) 0 else lengthBytes, labelSymbol = loopLabel), null)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=indexReg, immediate = if(lengthBytes==256) 0 else lengthBytes)
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it += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel)
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}
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}
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}
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}
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@ -608,7 +612,8 @@ class IRCodeGen(
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result += labelFirstChunk(translateNode(forLoop.statements), loopLabel)
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val chunk2 = addConstMem(loopvarDtIr, null, loopvarSymbol, iterable.step)
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chunk2 += IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol)
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chunk2 += IRInstruction(Opcode.BNE, loopvarDtIr, reg1 = indexReg, immediate = rangeEndExclusiveWrapped, labelSymbol = loopLabel)
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chunk2 += IRInstruction(Opcode.CMPI, loopvarDtIr, reg1 = indexReg, immediate = rangeEndExclusiveWrapped)
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chunk2 += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel)
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result += chunk2
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return result
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}
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@ -973,10 +978,13 @@ class IRCodeGen(
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0)
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it += branchInstr(goto, Opcode.BSTEQ)
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}
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"!=" -> {
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0)
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it += branchInstr(goto, Opcode.BSTNE)
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}
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else -> {
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// TODO: the old list of operators, still to be converted
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val gotoOpcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> Opcode.BLTS
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">" -> Opcode.BGTS
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"<=" -> Opcode.BLES
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@ -1029,10 +1037,13 @@ class IRCodeGen(
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = leftTr.resultReg, immediate = 0), null)
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addInstr(result, branchInstr(goto, Opcode.BSTEQ), null)
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}
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"!=" -> {
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = leftTr.resultReg, immediate = 0), null)
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addInstr(result, branchInstr(goto, Opcode.BSTNE), null)
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}
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else -> {
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// TODO: to-be converted operators
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val opcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> if (signed) Opcode.BLTS else Opcode.BLT
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">" -> if (signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if (signed) Opcode.BLES else Opcode.BLE
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@ -1060,12 +1071,10 @@ class IRCodeGen(
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if(condition==null) {
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val tr = expressionEval.translateExpression(ifElse.condition)
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result += tr.chunks
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if (goto.address != null)
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addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, address = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, labelSymbol = goto.identifier!!.name), null)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, irDtLeft, reg1 = tr.resultReg, immediate = 0)
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it += branchInstr(goto, Opcode.BSTNE)
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}
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} else {
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val leftTr = expressionEval.translateExpression(condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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@ -1078,10 +1087,13 @@ class IRCodeGen(
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = firstReg, immediate = number), null)
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addInstr(result, branchInstr(goto, Opcode.BSTEQ), null)
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}
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"!=" -> {
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = firstReg, immediate = number), null)
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addInstr(result, branchInstr(goto, Opcode.BSTNE), null)
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}
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else -> {
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// TODO: to-be converted operators
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val opcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> if(signed) Opcode.BLTS else Opcode.BLT
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">" -> if(signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if(signed) Opcode.BLES else Opcode.BLE
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@ -1165,7 +1177,10 @@ class IRCodeGen(
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightFpReg)
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}
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"==" -> {
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elseBranch = Opcode.BSTNE
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useCmpi = true
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}
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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@ -1183,7 +1198,10 @@ class IRCodeGen(
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compResultReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"==" -> {
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elseBranch = Opcode.BSTNE
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useCmpi = true
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}
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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@ -1273,7 +1291,10 @@ class IRCodeGen(
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val elseBranch: Opcode
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var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"==" -> {
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elseBranch = Opcode.BSTNE
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useCmpi = true
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}
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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@ -1322,7 +1343,10 @@ class IRCodeGen(
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val elseBranch: Opcode
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var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"==" -> {
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elseBranch = Opcode.BSTNE
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useCmpi = true
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}
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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@ -1593,8 +1617,8 @@ class IRCodeGen(
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}
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result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg)
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it += IRInstruction(Opcode.BNE, irDt, reg1 = countTr.resultReg, immediate = 0, labelSymbol = repeatLabel)
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it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg) // sets status bits
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it += IRInstruction(Opcode.BSTNE, labelSymbol = repeatLabel)
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}
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result += IRCodeChunk(skipRepeatLabel, null)
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return result
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@ -3,10 +3,12 @@
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main {
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sub start() {
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float xx = 10.1
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ubyte yy= xx==10.1
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txt.print_ub(yy)
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if xx==10.1
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txt.print("equal")
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float x=10
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float y=20
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bool r = x!=y
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txt.print_ub(r)
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repeat 4 {
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txt.print(".")
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}
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}
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}
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@ -85,7 +85,6 @@ bstvc address - branch to location if Status bit Overf
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bstvs address - branch to location if Status bit Overflow is set
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beqr reg1, reg2, address - jump to location in program given by location, if reg1 == reg2
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bner reg1, reg2, address - jump to location in program given by location, if reg1 != reg2
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bne reg1, value, address - jump to location in program given by location, if reg1 != immediate value
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bgt reg1, value, address - jump to location in program given by location, if reg1 > immediate value (unsigned)
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bgts reg1, value, address - jump to location in program given by location, if reg1 > immediate value (signed)
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bgtr reg1, reg2, address - jump to location in program given by location, if reg1 > reg2 (unsigned)
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@ -262,7 +261,6 @@ enum class Opcode {
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BSTVS,
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BEQR,
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BNER,
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BNE,
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BGTR,
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BGT,
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BLT,
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@ -407,7 +405,6 @@ val OpcodesThatBranch = setOf(
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Opcode.BSTVS,
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Opcode.BEQR,
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Opcode.BNER,
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Opcode.BNE,
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Opcode.BGTR,
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Opcode.BGT,
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Opcode.BLT,
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@ -557,7 +554,6 @@ val instructionFormats = mutableMapOf(
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Opcode.BSTVS to InstructionFormat.from("N,<a"),
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Opcode.BEQR to InstructionFormat.from("BW,<r1,<r2,<a"),
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Opcode.BNER to InstructionFormat.from("BW,<r1,<r2,<a"),
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Opcode.BNE to InstructionFormat.from("BW,<r1,<i,<a"),
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Opcode.BGTR to InstructionFormat.from("BW,<r1,<r2,<a"),
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Opcode.BGT to InstructionFormat.from("BW,<r1,<i,<a"),
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Opcode.BLT to InstructionFormat.from("BW,<r1,<i,<a"),
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@ -197,7 +197,6 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.BGTSR -> InsBGTSR(ins)
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Opcode.BGER -> InsBGER(ins)
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Opcode.BGESR -> InsBGESR(ins)
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Opcode.BNE -> InsBNE(ins)
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Opcode.BGT -> InsBGT(ins)
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Opcode.BLT -> InsBLT(ins)
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Opcode.BGTS -> InsBGTS(ins)
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@ -686,14 +685,6 @@ class VirtualMachine(irProgram: IRProgram) {
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nextPc()
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}
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private fun InsBNE(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsImmU(i)
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if(left!=right)
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branchTo(i)
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else
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nextPc()
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}
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private fun InsBGTR(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsU(i)
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if(left>right)
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