diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt index 6beaa6a6d..355a57d85 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt @@ -565,12 +565,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1) it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg) - if (notEquals) { - it += IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=valueReg, immediate = 0, labelSymbol = label) - } else { - it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0) - it += IRInstruction(Opcode.BSTEQ, labelSymbol = label) - } + it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0) + it += if (notEquals) + IRInstruction(Opcode.BSTNE, labelSymbol = label) + else + IRInstruction(Opcode.BSTEQ, labelSymbol = label) it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0) } result += IRCodeChunk(label, null) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt index 0ebea6592..cff24e27c 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt @@ -499,7 +499,8 @@ class IRCodeGen( result += translateNode(forLoop.statements) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexReg) - it += IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=indexReg, immediate = if(iterableLength==256) 0 else iterableLength, labelSymbol = loopLabel) + it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=indexReg, immediate = if(iterableLength==256) 0 else iterableLength) + it += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel) } } else -> { @@ -514,7 +515,10 @@ class IRCodeGen( } result += translateNode(forLoop.statements) result += addConstReg(IRDataType.BYTE, indexReg, elementSize) - addInstr(result, IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=indexReg, immediate = if(lengthBytes==256) 0 else lengthBytes, labelSymbol = loopLabel), null) + result += IRCodeChunk(null, null).also { + it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=indexReg, immediate = if(lengthBytes==256) 0 else lengthBytes) + it += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel) + } } } } @@ -608,7 +612,8 @@ class IRCodeGen( result += labelFirstChunk(translateNode(forLoop.statements), loopLabel) val chunk2 = addConstMem(loopvarDtIr, null, loopvarSymbol, iterable.step) chunk2 += IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol) - chunk2 += IRInstruction(Opcode.BNE, loopvarDtIr, reg1 = indexReg, immediate = rangeEndExclusiveWrapped, labelSymbol = loopLabel) + chunk2 += IRInstruction(Opcode.CMPI, loopvarDtIr, reg1 = indexReg, immediate = rangeEndExclusiveWrapped) + chunk2 += IRInstruction(Opcode.BSTNE, labelSymbol = loopLabel) result += chunk2 return result } @@ -973,10 +978,13 @@ class IRCodeGen( it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0) it += branchInstr(goto, Opcode.BSTEQ) } + "!=" -> { + it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0) + it += branchInstr(goto, Opcode.BSTNE) + } else -> { // TODO: the old list of operators, still to be converted val gotoOpcode = when (condition.operator) { - "!=" -> Opcode.BNE "<" -> Opcode.BLTS ">" -> Opcode.BGTS "<=" -> Opcode.BLES @@ -1029,10 +1037,13 @@ class IRCodeGen( addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = leftTr.resultReg, immediate = 0), null) addInstr(result, branchInstr(goto, Opcode.BSTEQ), null) } + "!=" -> { + addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = leftTr.resultReg, immediate = 0), null) + addInstr(result, branchInstr(goto, Opcode.BSTNE), null) + } else -> { // TODO: to-be converted operators val opcode = when (condition.operator) { - "!=" -> Opcode.BNE "<" -> if (signed) Opcode.BLTS else Opcode.BLT ">" -> if (signed) Opcode.BGTS else Opcode.BGT "<=" -> if (signed) Opcode.BLES else Opcode.BLE @@ -1060,12 +1071,10 @@ class IRCodeGen( if(condition==null) { val tr = expressionEval.translateExpression(ifElse.condition) result += tr.chunks - if (goto.address != null) - addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, address = goto.address?.toInt()), null) - else if (goto.generatedLabel != null) - addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, labelSymbol = goto.generatedLabel), null) - else - addInstr(result, IRInstruction(Opcode.BNE, irDtLeft, reg1 = tr.resultReg, immediate = 0, labelSymbol = goto.identifier!!.name), null) + result += IRCodeChunk(null, null).also { + it += IRInstruction(Opcode.CMPI, irDtLeft, reg1 = tr.resultReg, immediate = 0) + it += branchInstr(goto, Opcode.BSTNE) + } } else { val leftTr = expressionEval.translateExpression(condition.left) addToResult(result, leftTr, leftTr.resultReg, -1) @@ -1078,10 +1087,13 @@ class IRCodeGen( addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = firstReg, immediate = number), null) addInstr(result, branchInstr(goto, Opcode.BSTEQ), null) } + "!=" -> { + addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = firstReg, immediate = number), null) + addInstr(result, branchInstr(goto, Opcode.BSTNE), null) + } else -> { // TODO: to-be converted operators val opcode = when (condition.operator) { - "!=" -> Opcode.BNE "<" -> if(signed) Opcode.BLTS else Opcode.BLT ">" -> if(signed) Opcode.BGTS else Opcode.BGT "<=" -> if(signed) Opcode.BLES else Opcode.BLE @@ -1165,7 +1177,10 @@ class IRCodeGen( it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightFpReg) } when (condition.operator) { - "==" -> elseBranch = Opcode.BNE + "==" -> { + elseBranch = Opcode.BSTNE + useCmpi = true + } "!=" -> { elseBranch = Opcode.BSTEQ useCmpi = true @@ -1183,7 +1198,10 @@ class IRCodeGen( compResultReg = tr.resultReg addToResult(result, tr, tr.resultReg, -1) when (condition.operator) { - "==" -> elseBranch = Opcode.BNE + "==" -> { + elseBranch = Opcode.BSTNE + useCmpi = true + } "!=" -> { elseBranch = Opcode.BSTEQ useCmpi = true @@ -1273,7 +1291,10 @@ class IRCodeGen( val elseBranch: Opcode var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already when (condition.operator) { - "==" -> elseBranch = Opcode.BNE + "==" -> { + elseBranch = Opcode.BSTNE + useCmpi = true + } "!=" -> { elseBranch = Opcode.BSTEQ useCmpi = true @@ -1322,7 +1343,10 @@ class IRCodeGen( val elseBranch: Opcode var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already when (condition.operator) { - "==" -> elseBranch = Opcode.BNE + "==" -> { + elseBranch = Opcode.BSTNE + useCmpi = true + } "!=" -> { elseBranch = Opcode.BSTEQ useCmpi = true @@ -1593,8 +1617,8 @@ class IRCodeGen( } result += labelFirstChunk(translateNode(repeat.statements), repeatLabel) result += IRCodeChunk(null, null).also { - it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg) - it += IRInstruction(Opcode.BNE, irDt, reg1 = countTr.resultReg, immediate = 0, labelSymbol = repeatLabel) + it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg) // sets status bits + it += IRInstruction(Opcode.BSTNE, labelSymbol = repeatLabel) } result += IRCodeChunk(skipRepeatLabel, null) return result diff --git a/examples/test.p8 b/examples/test.p8 index 8d8651e7f..37adbbdca 100644 --- a/examples/test.p8 +++ b/examples/test.p8 @@ -3,10 +3,12 @@ main { sub start() { - float xx = 10.1 - ubyte yy= xx==10.1 - txt.print_ub(yy) - if xx==10.1 - txt.print("equal") + float x=10 + float y=20 + bool r = x!=y + txt.print_ub(r) + repeat 4 { + txt.print(".") + } } } diff --git a/intermediate/src/prog8/intermediate/IRInstructions.kt b/intermediate/src/prog8/intermediate/IRInstructions.kt index 6b2648c00..604e697fe 100644 --- a/intermediate/src/prog8/intermediate/IRInstructions.kt +++ b/intermediate/src/prog8/intermediate/IRInstructions.kt @@ -85,7 +85,6 @@ bstvc address - branch to location if Status bit Overf bstvs address - branch to location if Status bit Overflow is set beqr reg1, reg2, address - jump to location in program given by location, if reg1 == reg2 bner reg1, reg2, address - jump to location in program given by location, if reg1 != reg2 -bne reg1, value, address - jump to location in program given by location, if reg1 != immediate value bgt reg1, value, address - jump to location in program given by location, if reg1 > immediate value (unsigned) bgts reg1, value, address - jump to location in program given by location, if reg1 > immediate value (signed) bgtr reg1, reg2, address - jump to location in program given by location, if reg1 > reg2 (unsigned) @@ -262,7 +261,6 @@ enum class Opcode { BSTVS, BEQR, BNER, - BNE, BGTR, BGT, BLT, @@ -407,7 +405,6 @@ val OpcodesThatBranch = setOf( Opcode.BSTVS, Opcode.BEQR, Opcode.BNER, - Opcode.BNE, Opcode.BGTR, Opcode.BGT, Opcode.BLT, @@ -557,7 +554,6 @@ val instructionFormats = mutableMapOf( Opcode.BSTVS to InstructionFormat.from("N, InsBGTSR(ins) Opcode.BGER -> InsBGER(ins) Opcode.BGESR -> InsBGESR(ins) - Opcode.BNE -> InsBNE(ins) Opcode.BGT -> InsBGT(ins) Opcode.BLT -> InsBLT(ins) Opcode.BGTS -> InsBGTS(ins) @@ -686,14 +685,6 @@ class VirtualMachine(irProgram: IRProgram) { nextPc() } - private fun InsBNE(i: IRInstruction) { - val (left: UInt, right: UInt) = getBranchOperandsImmU(i) - if(left!=right) - branchTo(i) - else - nextPc() - } - private fun InsBGTR(i: IRInstruction) { val (left: UInt, right: UInt) = getBranchOperandsU(i) if(left>right)