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https://github.com/irmen/prog8.git
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fix broken optimization for wordvar - value expressions
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@@ -1438,10 +1438,9 @@ internal class AssignmentAsmGen(
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} else if(dt.isWord || dt.isPointer) {
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} else if(dt.isWord || dt.isPointer) {
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fun doAddOrSubWordExpr() {
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fun doAddOrSubWordExpr() {
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if(expr.left is PtIdentifier) {
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if(expr.operator=="+" && expr.left.type.isWord && expr.left is PtIdentifier) {
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val symname = asmgen.asmVariableName(expr.left as PtIdentifier)
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val symname = asmgen.asmVariableName(expr.left as PtIdentifier)
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assignExpressionToRegister(expr.right, RegisterOrPair.AY, dt.isSigned)
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assignExpressionToRegister(expr.right, RegisterOrPair.AY, expr.right.type.isSigned)
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if(expr.operator=="+")
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asmgen.out("""
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asmgen.out("""
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clc
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clc
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adc $symname
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adc $symname
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@@ -1450,7 +1449,10 @@ internal class AssignmentAsmGen(
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adc $symname+1
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adc $symname+1
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tay
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tay
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txa""")
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txa""")
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else
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}
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else if(expr.operator=="-" && expr.right.type.isWord && expr.right is PtIdentifier) {
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val symname = asmgen.asmVariableName(expr.right as PtIdentifier)
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, expr.left.type.isSigned)
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asmgen.out("""
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asmgen.out("""
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sec
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sec
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sbc $symname
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sbc $symname
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@@ -1603,7 +1605,7 @@ internal class AssignmentAsmGen(
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if(right.type.isSigned) {
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if(right.type.isSigned) {
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// we need to sign extend, do this via temporary word variable
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// we need to sign extend, do this via temporary word variable
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asmgen.assignExpressionToVariable(right, "P8ZP_SCRATCH_W1", DataType.WORD)
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asmgen.assignExpressionToVariable(right, "P8ZP_SCRATCH_W1", DataType.WORD)
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assignExpressionToRegister(left, RegisterOrPair.AY, dt.isSigned)
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assignExpressionToRegister(left, RegisterOrPair.AY, left.type.isSigned)
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if(expr.operator=="+") {
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if(expr.operator=="+") {
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asmgen.out("""
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asmgen.out("""
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clc
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clc
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@@ -1624,7 +1626,7 @@ internal class AssignmentAsmGen(
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txa""")
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txa""")
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}
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}
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} else {
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} else {
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assignExpressionToRegister(left, RegisterOrPair.AY, dt.isSigned)
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assignExpressionToRegister(left, RegisterOrPair.AY, left.type.isSigned)
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val castedSymname = asmgen.asmVariableName(castedValue)
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val castedSymname = asmgen.asmVariableName(castedValue)
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if (expr.operator == "+")
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if (expr.operator == "+")
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asmgen.out("""
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asmgen.out("""
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@@ -1,8 +1,7 @@
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TODO
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TODO
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====
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====
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SIZE REGRESSION: rockrunner is a bit larger than with 11.4.1
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SIZE REGRESSION: rockrunner is a few dozen bytes larger than with 11.4.1
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BUG: rockrunner level exit sound doesn't play anymore (11.4.1 was still ok) (can test with demo and warp)
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not all source lines are correctly reported in the IR file,
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not all source lines are correctly reported in the IR file,
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@@ -1,10 +1,14 @@
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main {
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%import textio
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struct element {
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%zeropage basicsafe
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word y
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}
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main {
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sub start() {
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sub start() {
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^^element zp_element = 20000
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uword @shared z = 100
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zp_element.y = cx16.r0L as byte
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ubyte @shared x = 200
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for x in 15 downto 1 {
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txt.print_uw(x*$0002-z) ; TODO fix 6502 optimization bug
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txt.nl()
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}
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}
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}
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}
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}
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@@ -111,7 +111,7 @@ private fun optimizeBinaryExpressions(program: PtProgram, options: CompilationOp
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val typecast=node.left as? PtTypeCast
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val typecast=node.left as? PtTypeCast
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if(typecast!=null && typecast.type.isWord && typecast.value is PtIdentifier) {
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if(typecast!=null && typecast.type.isWord && typecast.value is PtIdentifier) {
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val addition = node.parent as? PtBinaryExpression
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val addition = node.parent as? PtBinaryExpression
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if(addition!=null && (addition.operator=="+" || addition.operator=="-") && addition.type.isWord) {
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if(addition!=null && addition.operator=="+" && addition.type.isWord) {
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// word + (byte<<1 as uword) (== word + byte*2) --> (word + (byte as word)) + (byte as word)
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// word + (byte<<1 as uword) (== word + byte*2) --> (word + (byte as word)) + (byte as word)
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val parent = addition.parent
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val parent = addition.parent
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val index = parent.children.indexOf(addition)
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val index = parent.children.indexOf(addition)
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