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incrdecr codegen
This commit is contained in:
parent
a560982b7e
commit
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@ -5,12 +5,12 @@ This is the assembly code generator (from the parse tree)
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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"""
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"""
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import contextlib
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import contextlib
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import math
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import math
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import attr
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from typing import Set, Callable
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from typing import Set, Callable
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from ..datatypes import FLOAT_MAX_POSITIVE, FLOAT_MAX_NEGATIVE
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from ..datatypes import FLOAT_MAX_POSITIVE, FLOAT_MAX_NEGATIVE
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from ..plyparse import Scope
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from ..plyparse import Scope, AstNode
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from ..compile import Zeropage
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from ..compile import Zeropage
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@ -18,6 +18,14 @@ class CodeError(Exception):
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pass
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pass
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@attr.s(repr=False, cmp=False)
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class Context:
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out = attr.ib(type=Callable)
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stmt = attr.ib(type=AstNode)
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scope = attr.ib(type=Scope)
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floats_enabled = attr.ib(type=bool)
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def to_hex(number: int) -> str:
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def to_hex(number: int) -> str:
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# 0..15 -> "0".."15"
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# 0..15 -> "0".."15"
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# 16..255 -> "$10".."$ff"
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# 16..255 -> "$10".."$ff"
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@ -7,20 +7,24 @@ Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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from typing import Callable
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from typing import Callable
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from ..plyparse import Scope, Assignment, AugAssignment, Register, LiteralValue, SymbolName, VarDef
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from ..plyparse import Scope, Assignment, AugAssignment, Register, LiteralValue, SymbolName, VarDef
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from . import CodeError, preserving_registers, to_hex
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from . import CodeError, preserving_registers, to_hex, Context
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from ..datatypes import REGISTER_BYTES, REGISTER_WORDS, VarType, DataType
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from ..datatypes import REGISTER_BYTES, VarType
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from ..compile import Zeropage
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from ..compile import Zeropage
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def generate_assignment(out: Callable, stmt: Assignment, scope: Scope) -> None:
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def generate_assignment(ctx: Context) -> None:
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out("\v\t\t\t; " + stmt.lineref)
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assert isinstance(ctx.stmt, Assignment)
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out("\v; @todo assignment")
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ctx.out("\v\t\t\t; " + ctx.stmt.lineref)
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ctx.out("\v; @todo assignment")
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# @todo assignment
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# @todo assignment
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def generate_aug_assignment(out: Callable, stmt: AugAssignment, scope: Scope) -> None:
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def generate_aug_assignment(ctx: Context) -> None:
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# for instance: value += 3 (value = 0-255 for now)
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# for instance: value += 3 (value = 0-255 for now)
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# left: Register, SymbolName, or Dereference. right: Expression/LiteralValue
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# left: Register, SymbolName, or Dereference. right: Expression/LiteralValue
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out = ctx.out
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stmt = ctx.stmt
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assert isinstance(stmt, AugAssignment)
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out("\v\t\t\t; " + stmt.lineref)
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out("\v\t\t\t; " + stmt.lineref)
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lvalue = stmt.left
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lvalue = stmt.left
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rvalue = stmt.right
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rvalue = stmt.right
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@ -28,23 +32,23 @@ def generate_aug_assignment(out: Callable, stmt: AugAssignment, scope: Scope) ->
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if isinstance(rvalue, LiteralValue):
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if isinstance(rvalue, LiteralValue):
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if type(rvalue.value) is int:
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if type(rvalue.value) is int:
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if 0 <= rvalue.value <= 255:
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if 0 <= rvalue.value <= 255:
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_generate_aug_reg_constant_int(out, lvalue, stmt.operator, rvalue.value, "", scope)
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_generate_aug_reg_constant_int(out, lvalue, stmt.operator, rvalue.value, "", ctx.scope)
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else:
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else:
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raise CodeError("aug. assignment value must be 0..255", rvalue)
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raise CodeError("aug. assignment value must be 0..255", rvalue)
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else:
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else:
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raise CodeError("constant integer literal or variable required for now", rvalue) # XXX
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raise CodeError("constant integer literal or variable required for now", rvalue) # XXX
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elif isinstance(rvalue, SymbolName):
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elif isinstance(rvalue, SymbolName):
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symdef = scope.lookup(rvalue.name)
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symdef = ctx.scope.lookup(rvalue.name)
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if isinstance(symdef, VarDef) and symdef.vartype == VarType.CONST and symdef.datatype.isinteger():
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if isinstance(symdef, VarDef) and symdef.vartype == VarType.CONST and symdef.datatype.isinteger():
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if 0 <= symdef.value.const_value() <= 255: # type: ignore
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if 0 <= symdef.value.const_value() <= 255: # type: ignore
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_generate_aug_reg_constant_int(out, lvalue, stmt.operator, 0, symdef.name, scope)
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_generate_aug_reg_constant_int(out, lvalue, stmt.operator, 0, symdef.name, ctx.scope)
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else:
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else:
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raise CodeError("aug. assignment value must be 0..255", rvalue)
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raise CodeError("aug. assignment value must be 0..255", rvalue)
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else:
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else:
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raise CodeError("constant integer literal or variable required for now", rvalue) # XXX
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raise CodeError("constant integer literal or variable required for now", rvalue) # XXX
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elif isinstance(rvalue, Register):
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elif isinstance(rvalue, Register):
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# @todo check value range (single register; 0-255) @todo support combined registers
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# @todo check value range (single register; 0-255) @todo support combined registers
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_generate_aug_reg_reg(out, lvalue, stmt.operator, rvalue, scope)
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_generate_aug_reg_reg(out, lvalue, stmt.operator, rvalue, ctx.scope)
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else:
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else:
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# @todo Register += symbolname / dereference , _generate_aug_reg_mem?
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# @todo Register += symbolname / dereference , _generate_aug_reg_mem?
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raise CodeError("invalid rvalue for aug. assignment on register", rvalue)
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raise CodeError("invalid rvalue for aug. assignment on register", rvalue)
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@ -5,13 +5,17 @@ This is the code generator for gotos and subroutine calls.
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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"""
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"""
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from typing import Callable
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from ..plyparse import Goto, SubCall
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from ..plyparse import Goto, SubCall
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from . import Context
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def generate_goto(out: Callable, stmt: Goto) -> None:
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def generate_goto(ctx: Context) -> None:
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stmt = ctx.stmt
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assert isinstance(stmt, Goto)
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pass # @todo
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pass # @todo
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def generate_subcall(out: Callable, stmt: SubCall) -> None:
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def generate_subcall(ctx: Context) -> None:
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stmt = ctx.stmt
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assert isinstance(stmt, SubCall)
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pass # @todo
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pass # @todo
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@ -11,7 +11,7 @@ from typing import TextIO, Callable, no_type_check
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from ..plylex import print_bold
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from ..plylex import print_bold
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from ..plyparse import Module, Scope, ProgramFormat, Block, Directive, VarDef, Label, Subroutine, AstNode, ZpOptions, \
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from ..plyparse import Module, Scope, ProgramFormat, Block, Directive, VarDef, Label, Subroutine, AstNode, ZpOptions, \
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InlineAssembly, Return, Register, Goto, SubCall, Assignment, AugAssignment, IncrDecr, AssignmentTargets
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InlineAssembly, Return, Register, Goto, SubCall, Assignment, AugAssignment, IncrDecr, AssignmentTargets
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from . import CodeError, to_hex, to_mflpt5
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from . import CodeError, to_hex, to_mflpt5, Context
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from .variables import generate_block_init, generate_block_vars
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from .variables import generate_block_init, generate_block_vars
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from .assignment import generate_assignment, generate_aug_assignment
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from .assignment import generate_assignment, generate_aug_assignment
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from .calls import generate_goto, generate_subcall
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from .calls import generate_goto, generate_subcall
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@ -131,6 +131,7 @@ class AssemblyGenerator:
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# there's no code in the zero page block.
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# there's no code in the zero page block.
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out("\v.pend\n")
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out("\v.pend\n")
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for block in sorted(self.module.all_nodes(Block), key=lambda b: b.address or 0):
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for block in sorted(self.module.all_nodes(Block), key=lambda b: b.address or 0):
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ctx = Context(out=out, stmt=None, scope=block.scope, floats_enabled=self.floats_enabled)
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if block.name == "ZP":
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if block.name == "ZP":
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continue # already processed
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continue # already processed
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self.cur_block = block
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self.cur_block = block
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@ -153,7 +154,8 @@ class AssemblyGenerator:
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for stmt in block.scope.nodes:
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for stmt in block.scope.nodes:
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if isinstance(stmt, (VarDef, Subroutine)):
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if isinstance(stmt, (VarDef, Subroutine)):
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continue # should have been handled already or will be later
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continue # should have been handled already or will be later
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self.generate_statement(out, stmt, block.scope)
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ctx.stmt = stmt
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self.generate_statement(ctx)
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if block.name == "main" and isinstance(stmt, Label) and stmt.name == "start":
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if block.name == "main" and isinstance(stmt, Label) and stmt.name == "start":
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# make sure the main.start routine clears the decimal and carry flags as first steps
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# make sure the main.start routine clears the decimal and carry flags as first steps
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out("\vcld\n\vclc\n\vclv")
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out("\vcld\n\vclc\n\vclv")
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@ -170,8 +172,8 @@ class AssemblyGenerator:
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out("\v; params: {}\n\v; returns: {} clobbers: {}".format(params or "-", returns or "-", clobbers or "-"))
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out("\v; params: {}\n\v; returns: {} clobbers: {}".format(params or "-", returns or "-", clobbers or "-"))
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cur_block = self.cur_block
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cur_block = self.cur_block
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self.cur_block = subdef.scope
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self.cur_block = subdef.scope
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for stmt in subdef.scope.nodes:
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for ctx.stmt in subdef.scope.nodes:
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self.generate_statement(out, stmt, subdef.scope)
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self.generate_statement(ctx)
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self.cur_block = cur_block
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self.cur_block = cur_block
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out("")
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out("")
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out("; -- end block subroutines")
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out("; -- end block subroutines")
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@ -185,48 +187,52 @@ class AssemblyGenerator:
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out("\n\v.pend\n")
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out("\n\v.pend\n")
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@no_type_check
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@no_type_check
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def generate_statement(self, out: Callable, stmt: AstNode, scope: Scope) -> None:
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def generate_statement(self, ctx: Context) -> None:
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stmt = ctx.stmt
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if isinstance(stmt, Label):
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if isinstance(stmt, Label):
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out("\n{:s}\v\t\t; {:s}".format(stmt.name, stmt.lineref))
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ctx.out("\n{:s}\v\t\t; {:s}".format(stmt.name, stmt.lineref))
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elif isinstance(stmt, Return):
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elif isinstance(stmt, Return):
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if stmt.value_A:
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if stmt.value_A:
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reg = Register(name="A", sourceref=stmt.sourceref)
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reg = Register(name="A", sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(stmt.value_A)
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assignment.nodes.append(stmt.value_A)
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generate_assignment(out, assignment, scope)
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ctx.stmt = assignment
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generate_assignment(ctx)
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if stmt.value_X:
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if stmt.value_X:
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reg = Register(name="X", sourceref=stmt.sourceref)
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reg = Register(name="X", sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(stmt.value_X)
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assignment.nodes.append(stmt.value_X)
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generate_assignment(out, assignment, scope)
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ctx.stmt = assignment
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generate_assignment(ctx)
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if stmt.value_Y:
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if stmt.value_Y:
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reg = Register(name="Y", sourceref=stmt.sourceref)
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reg = Register(name="Y", sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment = Assignment(sourceref=stmt.sourceref)
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(AssignmentTargets(nodes=[reg], sourceref=stmt.sourceref))
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assignment.nodes.append(stmt.value_Y)
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assignment.nodes.append(stmt.value_Y)
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generate_assignment(out, assignment, scope)
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ctx.stmt = assignment
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out("\vrts")
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generate_assignment(ctx)
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ctx.out("\vrts")
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elif isinstance(stmt, InlineAssembly):
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elif isinstance(stmt, InlineAssembly):
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out("\n\v; inline asm, " + stmt.lineref)
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ctx.out("\n\v; inline asm, " + stmt.lineref)
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out(stmt.assembly)
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ctx.out(stmt.assembly)
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out("\v; end inline asm, " + stmt.lineref + "\n")
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ctx.out("\v; end inline asm, " + stmt.lineref + "\n")
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elif isinstance(stmt, IncrDecr):
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elif isinstance(stmt, IncrDecr):
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generate_incrdecr(out, stmt, scope, self.floats_enabled)
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generate_incrdecr(ctx)
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elif isinstance(stmt, Goto):
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elif isinstance(stmt, Goto):
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generate_goto(out, stmt)
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generate_goto(ctx)
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elif isinstance(stmt, SubCall):
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elif isinstance(stmt, SubCall):
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generate_subcall(out, stmt)
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generate_subcall(ctx)
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elif isinstance(stmt, Assignment):
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elif isinstance(stmt, Assignment):
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generate_assignment(out, stmt, scope)
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generate_assignment(ctx)
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elif isinstance(stmt, AugAssignment):
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elif isinstance(stmt, AugAssignment):
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generate_aug_assignment(out, stmt, scope)
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generate_aug_assignment(ctx)
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elif isinstance(stmt, Directive):
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elif isinstance(stmt, Directive):
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if stmt.name == "breakpoint":
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if stmt.name == "breakpoint":
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# put a marker in the source so that we can generate a list of breakpoints later
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# put a marker in the source so that we can generate a list of breakpoints later
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# this label is later extracted from the label dump file to turn it into a breakpoint instruction
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# this label is later extracted from the label dump file to turn it into a breakpoint instruction
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out("_il65_breakpoint_{:d}".format(id(stmt)))
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ctx.out("_il65_breakpoint_{:d}".format(id(stmt)))
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# other directives are ignored here
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# other directives are ignored here
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else:
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else:
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raise NotImplementedError("statement", stmt)
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raise NotImplementedError("statement", stmt)
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@ -7,13 +7,16 @@ is quite frequent and this generates assembly code tweaked for this case.
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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"""
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"""
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from typing import Callable
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from ..plyparse import VarType, VarDef, Register, IncrDecr, SymbolName, Dereference, LiteralValue, datatype_of
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from ..plyparse import Scope, VarType, VarDef, Register, IncrDecr, SymbolName, Dereference, LiteralValue, datatype_of
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from ..datatypes import DataType, REGISTER_BYTES
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from ..datatypes import DataType, REGISTER_BYTES
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from . import CodeError, preserving_registers, to_hex
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from . import CodeError, preserving_registers, to_hex, Context
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def generate_incrdecr(out: Callable, stmt: IncrDecr, scope: Scope, floats_enabled: bool) -> None:
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def generate_incrdecr(ctx: Context) -> None:
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out = ctx.out
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stmt = ctx.stmt
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scope = ctx.scope
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assert isinstance(stmt, IncrDecr)
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assert isinstance(stmt.howmuch, (int, float)) and stmt.howmuch >= 0
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assert isinstance(stmt.howmuch, (int, float)) and stmt.howmuch >= 0
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assert stmt.operator in ("++", "--")
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assert stmt.operator in ("++", "--")
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if stmt.howmuch == 0:
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if stmt.howmuch == 0:
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@ -185,7 +188,7 @@ def generate_incrdecr(out: Callable, stmt: IncrDecr, scope: Scope, floats_enable
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out("\vdec {:s}+1".format(what_str))
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out("\vdec {:s}+1".format(what_str))
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out("+")
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out("+")
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elif target.datatype == DataType.FLOAT:
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elif target.datatype == DataType.FLOAT:
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if not floats_enabled:
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if not ctx.floats_enabled:
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raise CodeError("floating point numbers not enabled via option")
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raise CodeError("floating point numbers not enabled via option")
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if stmt.howmuch == 1.0:
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if stmt.howmuch == 1.0:
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# special case for +/-1
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# special case for +/-1
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@ -224,7 +227,7 @@ def generate_incrdecr(out: Callable, stmt: IncrDecr, scope: Scope, floats_enable
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what = target.operand.name
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what = target.operand.name
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if stmt.howmuch == 1:
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if stmt.howmuch == 1:
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if target.datatype == DataType.FLOAT:
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if target.datatype == DataType.FLOAT:
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if not floats_enabled:
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if not ctx.floats_enabled:
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raise CodeError("floating point numbers not enabled via option")
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raise CodeError("floating point numbers not enabled via option")
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with preserving_registers({'A', 'X', 'Y'}, scope, out, loads_a_within=True):
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with preserving_registers({'A', 'X', 'Y'}, scope, out, loads_a_within=True):
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out("\vldx " + what)
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out("\vldx " + what)
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@ -236,19 +239,13 @@ def generate_incrdecr(out: Callable, stmt: IncrDecr, scope: Scope, floats_enable
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else:
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else:
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with preserving_registers({'A', 'Y'}, scope, out, loads_a_within=True):
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with preserving_registers({'A', 'Y'}, scope, out, loads_a_within=True):
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out("\vlda " + what)
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out("\vlda " + what)
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out("\vsta c64.SCRATCH_ZPWORD1")
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out("\vldy {:s}+1".format(what))
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out("\vlda {:s}+1".format(what))
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out("\vsta c64.SCRATCH_ZPWORD1+1")
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if target.datatype == DataType.BYTE:
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if target.datatype == DataType.BYTE:
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if stmt.operator == "++":
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out("\vclc" if stmt.operator == "++" else "\vsec")
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out("\vjsr il65_lib.incr_deref_byte")
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out("\vjsr il65_lib.incrdecr_deref_byte_reg_AY")
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else:
|
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||||||
out("\vjsr il65_lib.decr_deref_byte")
|
|
||||||
elif target.datatype == DataType.WORD:
|
elif target.datatype == DataType.WORD:
|
||||||
if stmt.operator == "++":
|
out("\vclc" if stmt.operator == "++" else "\vsec")
|
||||||
out("\vjsr il65_lib.incr_deref_word")
|
out("\vjsr il65_lib.incrdecr_deref_word_reg_AY")
|
||||||
else:
|
|
||||||
out("\vjsr il65_lib.decr_deref_word")
|
|
||||||
else:
|
else:
|
||||||
raise CodeError("cannot inc/decrement dereferenced literal of type " + str(target.datatype), stmt)
|
raise CodeError("cannot inc/decrement dereferenced literal of type " + str(target.datatype), stmt)
|
||||||
else:
|
else:
|
||||||
@ -258,10 +255,7 @@ def generate_incrdecr(out: Callable, stmt: IncrDecr, scope: Scope, floats_enable
|
|||||||
raise CodeError("can't dereference just a single register, need combined register", target)
|
raise CodeError("can't dereference just a single register, need combined register", target)
|
||||||
reg = target.operand.name
|
reg = target.operand.name
|
||||||
if stmt.howmuch == 1:
|
if stmt.howmuch == 1:
|
||||||
if stmt.operator == "++":
|
out("\vclc" if stmt.operator == "++" else "\vsec")
|
||||||
out("\vclc")
|
|
||||||
else:
|
|
||||||
out("\vsec")
|
|
||||||
if target.datatype == DataType.BYTE:
|
if target.datatype == DataType.BYTE:
|
||||||
with preserving_registers({'A', 'Y'}, scope, out, loads_a_within=True):
|
with preserving_registers({'A', 'Y'}, scope, out, loads_a_within=True):
|
||||||
out("\vjsr il65_lib.incrdecr_deref_byte_reg_" + reg)
|
out("\vjsr il65_lib.incrdecr_deref_byte_reg_" + reg)
|
||||||
|
15
todo.ill
15
todo.ill
@ -31,17 +31,16 @@ start:
|
|||||||
[$55 .float] ++
|
[$55 .float] ++
|
||||||
[screenm .float]--
|
[screenm .float]--
|
||||||
|
|
||||||
;[border] ++
|
[border] ++
|
||||||
;[border] ++
|
[border] ++
|
||||||
;[border] --
|
[border] --
|
||||||
[$d020] ++
|
[$d020] ++
|
||||||
[$d020] ++
|
[$d020] ++
|
||||||
[$d020] --
|
[$d020] --
|
||||||
;[border2] ++ ;@todo suport incr/decr on deref var WORD
|
[border2 .word] ++
|
||||||
;[border2] ++ ;@todo suport incr/decr on deref var WORD
|
[border2 .float] ++
|
||||||
;[border2] -- ;@todo suport incr/decr on deref var WORD
|
[border2] --
|
||||||
;[XY] ++
|
[XY] ++
|
||||||
;[XY] --
|
|
||||||
|
|
||||||
return 44.123
|
return 44.123
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user