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https://github.com/irmen/prog8.git
synced 2025-02-02 19:32:21 +00:00
tests for register args for normal subs
some warnings demoted into infos
This commit is contained in:
Irmen de Jong
parent
2e35f3c3a3
commit
d58f9f56c4
@ -347,7 +347,7 @@ internal class IfElseAsmGen(private val program: PtProgram,
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else
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translateIfElseBodies("beq", stmt)
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} else {
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errors.warn("SLOW FALLBACK FOR 'IF' CODEGEN - ask for support", stmt.position) // should not occur ;-)
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errors.info("SLOW FALLBACK FOR 'IF' CODEGEN - ask for support", stmt.position) // should not occur ;-)
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assignConditionValueToRegisterAndTest(stmt.condition)
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if(jumpAfterIf!=null)
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translateJumpElseBodies("bne", "beq", jumpAfterIf, stmt.elseScope)
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@ -796,13 +796,13 @@ class ExpressionSimplifier(private val program: Program, private val errors: IEr
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when (val targetDt = targetIDt.getOr(DataType.UNDEFINED)) {
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DataType.UBYTE, DataType.BYTE -> {
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if (amount >= 8) {
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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return NumericLiteral(targetDt, 0.0, expr.position)
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}
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}
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DataType.UWORD -> {
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if (amount >= 16) {
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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return NumericLiteral(targetDt, 0.0, expr.position)
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}
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else if(amount==8) {
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@ -819,7 +819,7 @@ class ExpressionSimplifier(private val program: Program, private val errors: IEr
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}
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DataType.WORD -> {
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if (amount >= 16) {
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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return NumericLiteral(targetDt, 0.0, expr.position)
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}
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else if(amount==8) {
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@ -856,7 +856,7 @@ class ExpressionSimplifier(private val program: Program, private val errors: IEr
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when (idt.getOr(DataType.UNDEFINED)) {
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DataType.UBYTE -> {
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if (amount >= 8) {
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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return NumericLiteral.optimalInteger(0, expr.position)
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}
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}
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@ -372,7 +372,7 @@ internal class AstChecker(private val program: Program,
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err("cannot redefine a built-in function")
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if(subroutine.parameters.size>6 && !subroutine.isAsmSubroutine && !subroutine.definingBlock.isInLibrary)
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errors.warn("subroutine has a large number of parameters, this is slow if called often", subroutine.position)
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errors.info("subroutine has a large number of parameters, this is slow if called often", subroutine.position)
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val uniqueNames = subroutine.parameters.asSequence().map { it.name }.toSet()
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if(uniqueNames.size!=subroutine.parameters.size)
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@ -235,9 +235,12 @@ class AstPreprocessor(val program: Program,
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registerParams
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.filter { it.name !in namesInSub && it.name !in existingAliases }
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.forEach {
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val regname = it.registerOrPair!!.asScopedNameVirtualReg(it.type)
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var alias = Alias(it.name, IdentifierReference(regname, it.position), it.position)
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mods += IAstModification.InsertFirst(alias, subroutine)
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if (it.registerOrPair in Cx16VirtualRegisters) {
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val regname = it.registerOrPair!!.asScopedNameVirtualReg(it.type)
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var alias = Alias(it.name, IdentifierReference(regname, it.position), it.position)
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mods += IAstModification.InsertFirst(alias, subroutine)
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} else
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errors.err("can only use R0-R15 as register param for normal subroutines", it.position)
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}
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}
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return mods
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@ -101,9 +101,9 @@ internal class BeforeAsmTypecastCleaner(val program: Program,
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if(shifts!=null) {
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val dt = expr.left.inferType(program)
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if(dt.istype(DataType.UBYTE) && shifts.number>=8.0)
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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if(dt.istype(DataType.UWORD) && shifts.number>=16.0)
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errors.warn("shift always results in 0", expr.position)
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errors.info("shift always results in 0", expr.position)
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if(shifts.number<=255.0 && shifts.type in WordDatatypes) {
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val byteVal = NumericLiteral(DataType.UBYTE, shifts.number, shifts.position)
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return listOf(IAstModification.ReplaceNode(expr.right, byteVal, expr))
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@ -84,7 +84,6 @@ internal class LiteralsToAutoVars(private val program: Program, private val erro
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val decl = elt.targetVarDecl(program)
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if(decl!=null && decl.splitArray) {
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// you can't take the adress of a split-word array.
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// instead of giving a fatal error, we remove the
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// instead of a fatal error, we give a warning and turn it back into a regular array.
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errors.warn("cannot take address of split word array - the array is turned back into a regular word array", decl.position)
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val normalArray = makeNormalArrayFromSplit(decl)
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@ -263,7 +263,7 @@ class TypecastsAdder(val program: Program, val options: CompilationOptions, val
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// warn about any implicit type casts to Float, because that may not be intended
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if(typecast.implicit && typecast.type.oneOf(DataType.FLOAT, DataType.ARRAY_F)) {
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if(options.floats)
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errors.warn("integer implicitly converted to float. Suggestion: use float literals, add an explicit cast, or revert to integer arithmetic", typecast.position)
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errors.info("integer implicitly converted to float. Suggestion: use float literals, add an explicit cast, or revert to integer arithmetic", typecast.position)
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else
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errors.err("integer implicitly converted to float but floating point is not enabled via options", typecast.position)
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}
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@ -131,9 +131,9 @@ class TestNumbers: FunSpec({
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val errors = ErrorReporterForTests(keepMessagesAfterReporting = true)
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compileText(C64Target(), true, src, writeAssembly = false, errors=errors) shouldNotBe null
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errors.errors.size shouldBe 0
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errors.warnings.size shouldBe 2
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errors.warnings[0] shouldContain "converted to float"
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errors.warnings[1] shouldContain "converted to float"
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errors.infos.size shouldBe 2
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errors.infos[0] shouldContain "converted to float"
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errors.infos[1] shouldContain "converted to float"
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}
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test("implicit float conversion error if not enabled") {
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@ -28,9 +28,9 @@ class TestAstChecks: FunSpec({
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val errors = ErrorReporterForTests(keepMessagesAfterReporting = true)
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compileText(C64Target(), true, text, writeAssembly = true, errors=errors) shouldNotBe null
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errors.errors.size shouldBe 0
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errors.warnings.size shouldBe 2
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errors.warnings[0] shouldContain "converted to float"
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errors.warnings[1] shouldContain "converted to float"
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errors.infos.size shouldBe 2
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errors.infos[0] shouldContain "converted to float"
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errors.infos[1] shouldContain "converted to float"
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}
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test("can't assign label or subroutine without using address-of") {
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@ -273,4 +273,81 @@ main {
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compileText(C64Target(), false, src, writeAssembly = false) shouldNotBe null
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compileText(C64Target(), true, src, writeAssembly = false) shouldNotBe null
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}
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test("reg params cannot be statusflag") {
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val src="""
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main {
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sub start() {
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faulty(false)
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}
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sub faulty(bool flag @Pc) {
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cx16.r0++
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}
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}"""
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// the syntax error is actually thrown by the parser, so we cannot catch it, but we know that there may not be a compilation result
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compileText(C64Target(), false, src, writeAssembly = false) shouldBe null
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}
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test("reg params cannot be cpu register") {
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val src="""
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main {
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sub start() {
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faulty(42)
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}
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sub faulty(byte arg @Y) {
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arg++
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}
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}"""
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val errors = ErrorReporterForTests()
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compileText(C64Target(), false, src, writeAssembly = false, errors = errors) shouldBe null
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errors.errors.size shouldBe 1
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errors.errors[0] shouldContain "can only use R0-R15"
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}
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test("reg params must be all different") {
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val src="""
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main {
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sub start() {
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faulty3(9999,55)
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}
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sub faulty3(uword arg @R1, ubyte arg2 @R1) {
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arg += arg2
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}
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}"""
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val errors = ErrorReporterForTests()
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compileText(C64Target(), false, src, writeAssembly = false, errors = errors) shouldBe null
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errors.errors.size shouldBe 1
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errors.errors[0] shouldContain "register is used multiple times"
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}
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test("reg params R0-R15 are ok") {
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val src="""
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main {
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sub start() {
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foo(42)
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bar(9999,55)
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}
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sub foo(ubyte arg @R2) {
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arg++
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}
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sub bar(uword arg @R0, ubyte arg2 @R1) {
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arg += arg2
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}
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}"""
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val errors = ErrorReporterForTests(keepMessagesAfterReporting = true)
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compileText(C64Target(), false, src, writeAssembly = false, errors = errors) shouldNotBe null
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errors.errors.size shouldBe 0
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errors.warnings.size shouldBe 2
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errors.warnings[0] shouldContain "footgun"
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errors.warnings[1] shouldContain "footgun"
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}
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})
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@ -2,12 +2,9 @@ TODO
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====
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document the @R0 - @R15 register support for normal subroutine parameters (footgun!)
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add unit tests for it too.
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make a compiler switch to disable footgun warnings
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turn some existing warnings into INFO
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what to do with bankof(): keep it? add another syntax like \`value or ^value to get the bank byte?
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add a function like addr() or lsw() to complement bnk() in getting easy access to the lower 16 bits of a long integer?
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-> added unary ^ operator as alternative to bankof()
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@ -21,8 +18,6 @@ add a function like addr() or lsw() to complement bnk() in getting easy access t
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Future Things and Ideas
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^^^^^^^^^^^^^^^^^^^^^^^
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- a way to specify subroutine params for normal (non-asmsub) subs to be in r0-r15 registers instead of allocating a new localvariable for them
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- the previous should give another footgun warning (the @dirty info should be a footgun warning/info as well). Need a switch to turn off footgun warnings.
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- something to reduce the need to use fully qualified names all the time. 'with' ? Or 'using <prefix>'?
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- on the C64: make the floating point routines @banked so that basic can be permanently banked out even if you use floats? But this will crash when the call is done from program code at $a000+
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- Libraries: improve ability to create library files in prog8; for instance there's still stuff injected into the start of the start() routine AND there is separate setup logic going on before calling it.
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@ -1,36 +1,29 @@
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%import textio
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%zeropage basicsafe
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main {
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sub start() {
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foo(42)
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foo2(42)
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bar(9999,55)
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bar2(9999,55)
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txt.nl()
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; faulty1(false)
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faulty2(42)
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faulty3(9999,55)
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}
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sub foo(ubyte arg) {
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txt.print_ub(arg)
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txt.nl()
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sub foo(ubyte arg @R2) {
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arg++
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}
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sub foo2(ubyte arg @R2) {
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txt.print_ub(arg)
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txt.nl()
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sub bar(uword arg @R0, ubyte arg2 @R1) {
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arg += arg2
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}
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sub bar(uword arg, ubyte arg2) {
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txt.print_uw(arg)
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txt.spc()
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txt.print_ub(arg2)
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txt.nl()
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; sub faulty1(bool flag @Pc) {
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; cx16.r0++
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; }
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sub faulty2(byte arg @Y) {
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arg++
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}
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sub bar2(uword arg @R0, ubyte arg2 @R1) {
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txt.print_uw(arg)
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txt.spc()
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txt.print_ub(arg2)
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txt.nl()
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sub faulty3(uword arg @R1, ubyte arg2 @R1) {
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arg += arg2
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}
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}
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