mirror of
https://github.com/irmen/prog8.git
synced 2024-07-25 13:29:03 +00:00
IR: more optimal branch instructions for comparisons against zero
This commit is contained in:
Irmen de Jong
parent
025183602f
commit
dc316fd7b4
@ -16,32 +16,28 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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return translateRegularAssign(assignment)
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}
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internal fun translate(augmentedAssign: PtAugmentedAssign): IRCodeChunks {
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if(augmentedAssign.target.children.single() is PtMachineRegister)
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internal fun translate(augAssign: PtAugmentedAssign): IRCodeChunks {
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if(augAssign.target.children.single() is PtMachineRegister)
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throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
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return translateInplaceAssign(augmentedAssign)
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}
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private fun translateInplaceAssign(assignment: PtAugmentedAssign): IRCodeChunks {
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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val ident = augAssign.target.identifier
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val memory = augAssign.target.memory
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val array = augAssign.target.array
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return if(ident!=null) {
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assignVarAugmented(ident.name, assignment)
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assignVarAugmented(ident.name, augAssign)
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} else if(memory != null) {
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if(memory.address is PtNumber)
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assignMemoryAugmented((memory.address as PtNumber).number.toInt(), assignment)
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assignMemoryAugmented((memory.address as PtNumber).number.toInt(), augAssign)
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else
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fallbackAssign(assignment)
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fallbackAssign(augAssign)
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} else if(array!=null) {
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// NOTE: naive fallback assignment here will sometimes generate code that loads the index value multiple times
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// in a register. It's way too much work to optimize that here - instead, we trust that the generated IL assembly
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// will be optimized later and have the double assignments removed.
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fallbackAssign(assignment)
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fallbackAssign(augAssign)
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} else {
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fallbackAssign(assignment)
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fallbackAssign(augAssign)
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}
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}
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@ -131,66 +127,70 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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private fun translateRegularAssign(assignment: PtAssignment): IRCodeChunks {
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// note: assigning array and string values is done via an explicit memcopy/stringcopy function call.
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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val targetIdent = assignment.target.identifier
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val targetMemory = assignment.target.memory
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val targetArray = assignment.target.array
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val vmDt = codeGen.irType(assignment.value.type)
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val result = mutableListOf<IRCodeChunkBase>()
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var resultRegister = -1
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var resultFpRegister = -1
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var valueRegister = -1
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var valueFpRegister = -1
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val zero = codeGen.isZero(assignment.value)
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if(!zero) {
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// calculate the assignment value
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if (vmDt == IRDataType.FLOAT) {
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val tr = expressionEval.translateExpression(assignment.value)
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resultFpRegister = tr.resultFpReg
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addToResult(result, tr, -1, tr.resultFpReg)
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valueFpRegister = tr.resultFpReg
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addToResult(result, tr, -1, valueFpRegister)
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} else {
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resultRegister = if (assignment.value is PtMachineRegister) {
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(assignment.value as PtMachineRegister).register
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if (assignment.value is PtMachineRegister) {
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valueRegister = (assignment.value as PtMachineRegister).register
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} else {
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val tr = expressionEval.translateExpression(assignment.value)
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addToResult(result, tr, tr.resultReg, -1)
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tr.resultReg
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valueRegister = tr.resultReg
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addToResult(result, tr, valueRegister, -1)
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}
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}
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}
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if(ident!=null) {
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if(targetIdent!=null) {
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val instruction = if(zero) {
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IRInstruction(Opcode.STOREZM, vmDt, labelSymbol = ident.name)
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IRInstruction(Opcode.STOREZM, vmDt, labelSymbol = targetIdent.name)
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} else {
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if (vmDt == IRDataType.FLOAT)
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IRInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, labelSymbol = ident.name)
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if (vmDt == IRDataType.FLOAT) {
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IRInstruction(Opcode.STOREM, vmDt, fpReg1 = valueFpRegister, labelSymbol = targetIdent.name)
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}
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else
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IRInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, labelSymbol = ident.name)
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IRInstruction(Opcode.STOREM, vmDt, reg1 = valueRegister, labelSymbol = targetIdent.name)
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}
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result += IRCodeChunk(null, null).also { it += instruction }
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return result
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}
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else if(array!=null) {
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val variable = array.variable.name
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val itemsize = codeGen.program.memsizer.memorySize(array.type)
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else if(targetArray!=null) {
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val variable = targetArray.variable.name
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val itemsize = codeGen.program.memsizer.memorySize(targetArray.type)
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if(array.variable.type==DataType.UWORD) {
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if(targetArray.variable.type==DataType.UWORD) {
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// indexing a pointer var instead of a real array or string
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if(itemsize!=1)
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throw AssemblyError("non-array var indexing requires bytes dt")
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if(array.index.type!=DataType.UBYTE)
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if(targetArray.index.type!=DataType.UBYTE)
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throw AssemblyError("non-array var indexing requires bytes index")
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val idxTr = expressionEval.translateExpression(array.index)
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addToResult(result, idxTr, idxTr.resultReg, -1)
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val tr = expressionEval.translateExpression(targetArray.index)
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val idxReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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val code = IRCodeChunk(null, null)
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if(zero) {
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// there's no STOREZIX instruction
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resultRegister = codeGen.registers.nextFree()
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code += IRInstruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=0)
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valueRegister = codeGen.registers.nextFree()
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code += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegister, value=0)
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}
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code += IRInstruction(Opcode.STOREIX, vmDt, reg1=resultRegister, reg2=idxTr.resultReg, labelSymbol = variable)
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code += IRInstruction(Opcode.STOREIX, vmDt, reg1=valueRegister, reg2=idxReg, labelSymbol = variable)
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result += code
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return result
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}
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val fixedIndex = constIntValue(array.index)
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val fixedIndex = constIntValue(targetArray.index)
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if(zero) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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@ -198,53 +198,55 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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result += chunk
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} else {
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val indexReg = codeGen.registers.nextFree()
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result += loadIndexReg(array, itemsize, indexReg)
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result += loadIndexReg(targetArray, itemsize, indexReg)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZX, vmDt, reg1=indexReg, labelSymbol = variable) }
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}
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} else {
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if(vmDt== IRDataType.FLOAT) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, labelSymbol = "$variable+$offset") }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, fpReg1 = valueFpRegister, labelSymbol = "$variable+$offset") }
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result += chunk
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} else {
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val indexReg = codeGen.registers.nextFree()
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result += loadIndexReg(array, itemsize, indexReg)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = indexReg, fpReg1 = resultFpRegister, labelSymbol = variable) }
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result += loadIndexReg(targetArray, itemsize, indexReg)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = indexReg, fpReg1 = valueFpRegister, labelSymbol = variable) }
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}
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} else {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, labelSymbol = "$variable+$offset") }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1 = valueRegister, labelSymbol = "$variable+$offset") }
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result += chunk
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} else {
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val indexReg = codeGen.registers.nextFree()
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result += loadIndexReg(array, itemsize, indexReg)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, labelSymbol = variable) }
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result += loadIndexReg(targetArray, itemsize, indexReg)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable) }
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}
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}
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}
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return result
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}
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else if(memory!=null) {
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require(vmDt== IRDataType.BYTE) { "must be byte type ${memory.position}"}
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else if(targetMemory!=null) {
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require(vmDt== IRDataType.BYTE) { "must be byte type ${targetMemory.position}"}
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if(zero) {
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if(memory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, vmDt, value=(memory.address as PtNumber).number.toInt()) }
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if(targetMemory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, vmDt, value=(targetMemory.address as PtNumber).number.toInt()) }
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result += chunk
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} else {
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val tr = expressionEval.translateExpression(memory.address)
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val tr = expressionEval.translateExpression(targetMemory.address)
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val addressReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=tr.resultReg) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) }
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}
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} else {
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if(memory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt()) }
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if(targetMemory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueRegister, value=(targetMemory.address as PtNumber).number.toInt()) }
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result += chunk
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} else {
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val tr = expressionEval.translateExpression(memory.address)
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val tr = expressionEval.translateExpression(targetMemory.address)
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val addressReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=tr.resultReg) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=valueRegister, reg2=addressReg) }
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}
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}
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@ -937,57 +937,100 @@ class IRCodeGen(
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else
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = goto.identifier!!.name)
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}
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return result
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} else {
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val leftTr = expressionEval.translateExpression(ifElse.condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val rightTr = expressionEval.translateExpression(ifElse.condition.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val opcode: Opcode
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val firstReg: Int
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val secondReg: Int
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when (ifElse.condition.operator) {
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"==" -> {
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opcode = Opcode.BEQ
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"!=" -> {
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opcode = Opcode.BNE
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"<" -> {
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// swapped '>'
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opcode = if (signed) Opcode.BGTS else Opcode.BGT
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firstReg = rightTr.resultReg
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secondReg = leftTr.resultReg
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}
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">" -> {
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opcode = if (signed) Opcode.BGTS else Opcode.BGT
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"<=" -> {
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// swapped '>='
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opcode = if (signed) Opcode.BGES else Opcode.BGE
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firstReg = rightTr.resultReg
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secondReg = leftTr.resultReg
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}
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">=" -> {
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opcode = if (signed) Opcode.BGES else Opcode.BGE
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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else -> throw AssemblyError("invalid comparison operator")
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val rightConst = ifElse.condition.right.asConstInteger()
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return if(rightConst==0)
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ifZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
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else {
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ifNonZeroIntThenJump(result, ifElse, signed, irDtLeft, goto)
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, value = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.identifier!!.name), null)
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}
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}
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private fun ifZeroIntThenJump(
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result: MutableList<IRCodeChunkBase>,
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ifElse: PtIfElse,
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signed: Boolean,
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irDtLeft: IRDataType,
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goto: PtJump
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): MutableList<IRCodeChunkBase> {
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val leftTr = expressionEval.translateExpression(ifElse.condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val opcode = when (ifElse.condition.operator) {
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"==" -> Opcode.BZ
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"!=" -> Opcode.BNZ
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"<" -> if (signed) Opcode.BLZS else throw AssemblyError("unsigned < 0 shouldn't occur in codegen")
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">" -> if (signed) Opcode.BGZS else throw AssemblyError("unsigned > 0 shouldn't occur in codegen")
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"<=" -> if (signed) Opcode.BLEZS else throw AssemblyError("unsigned <= 0 shouldn't occur in codegen")
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">=" -> if (signed) Opcode.BGEZS else throw AssemblyError("unsigned >= 0 shouldn't occur in codegen")
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else -> throw AssemblyError("invalid comparison operator")
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, value = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, labelSymbol = goto.identifier!!.name), null)
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return result
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}
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private fun ifNonZeroIntThenJump(
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result: MutableList<IRCodeChunkBase>,
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ifElse: PtIfElse,
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signed: Boolean,
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irDtLeft: IRDataType,
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goto: PtJump
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): MutableList<IRCodeChunkBase> {
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val leftTr = expressionEval.translateExpression(ifElse.condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val rightTr = expressionEval.translateExpression(ifElse.condition.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val opcode: Opcode
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val firstReg: Int
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val secondReg: Int
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when (ifElse.condition.operator) {
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"==" -> {
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opcode = Opcode.BEQ
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"!=" -> {
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opcode = Opcode.BNE
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"<" -> {
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// swapped '>'
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opcode = if (signed) Opcode.BGTS else Opcode.BGT
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firstReg = rightTr.resultReg
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secondReg = leftTr.resultReg
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}
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">" -> {
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opcode = if (signed) Opcode.BGTS else Opcode.BGT
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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"<=" -> {
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// swapped '>='
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opcode = if (signed) Opcode.BGES else Opcode.BGE
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firstReg = rightTr.resultReg
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secondReg = leftTr.resultReg
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}
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">=" -> {
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opcode = if (signed) Opcode.BGES else Opcode.BGE
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firstReg = leftTr.resultReg
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secondReg = rightTr.resultReg
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}
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else -> throw AssemblyError("invalid comparison operator")
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, value = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, reg2 = secondReg, labelSymbol = goto.identifier!!.name), null)
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return result
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}
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@ -386,7 +386,7 @@ main {
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val irProgram = IRFileReader().read(virtfile)
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val start = irProgram.blocks[0].children[0] as IRSubroutine
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val instructions = start.chunks.flatMap { c->c.instructions }
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instructions.size shouldBe 18
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instructions.size shouldBe 13
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instructions.last().opcode shouldBe Opcode.RETURN
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}
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