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fix resultregister crash
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parent
c098ad2b3b
commit
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@ -872,7 +872,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, signed, fcall.position, fcall.definingISub(), asmgen)
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assignAsmGen.assignRegisterByte(targetReg, CpuRegister.A, signed)
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assignAsmGen.assignRegisterByte(targetReg, CpuRegister.A, signed)
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}
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}
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}
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}
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@ -884,7 +884,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, signed, fcall.position, fcall.definingISub(), asmgen)
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assignAsmGen.assignRegisterpairWord(targetReg, RegisterOrPair.AY)
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assignAsmGen.assignRegisterpairWord(targetReg, RegisterOrPair.AY)
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}
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}
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}
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}
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@ -905,7 +905,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.A, targetReg)
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asmgen.assignRegister(RegisterOrPair.A, targetReg)
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}
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}
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} else if(fcall.type in WordDatatypes) {
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} else if(fcall.type in WordDatatypes) {
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@ -946,7 +946,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.AY, targetReg)
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asmgen.assignRegister(RegisterOrPair.AY, targetReg)
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}
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}
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} else {
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} else {
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@ -967,7 +967,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.A, targetReg)
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asmgen.assignRegister(RegisterOrPair.A, targetReg)
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}
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}
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} else if(fcall.type in WordDatatypes) {
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} else if(fcall.type in WordDatatypes) {
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@ -1008,7 +1008,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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if(resultToStack) {
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if(resultToStack) {
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | sty P8ESTACK_HI,x | dex")
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} else {
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} else {
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister!!, signed, fcall.position, fcall.definingISub(), asmgen)
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.AY, targetReg)
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asmgen.assignRegister(RegisterOrPair.AY, targetReg)
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}
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}
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} else {
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} else {
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