diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
index 06c5e11e1..f9e0e043f 100644
--- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
+++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
@@ -461,24 +461,22 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                     else
                         IRInstruction(Opcode.CALL, address = callTarget.address!!.toInt(), fcallArgs = FunctionCallArgs(argRegisters, returnRegSpec))
                 addInstr(result, call, null)
-
                 var finalReturnRegister = returnRegSpec?.registerNum ?: -1
 
-                if(fcall.parent is PtAssignment) {
+                if(fcall.parent is PtAssignment || fcall.parent is PtTypeCast) {
                     // look if the status flag bit should actually be returned as a 0/1 byte value in a result register (so it can be assigned)
                     if(statusFlagResult!=null && returnRegSpec!=null) {
                         // assign status flag bit to the return value register
-                        finalReturnRegister = codeGen.registers.nextFree()
+                        finalReturnRegister = returnRegSpec.registerNum
+                        if(finalReturnRegister<0)
+                            finalReturnRegister = codeGen.registers.nextFree()
                         when(statusFlagResult) {
                             Statusflag.Pc -> {
-                                result += IRCodeChunk(null, null).also {
-                                    it += IRInstruction(Opcode.LOAD, returnRegSpec.dt, reg1=finalReturnRegister, immediate = 0)
-                                    it += IRInstruction(Opcode.ROXL, returnRegSpec.dt, reg1=finalReturnRegister)
-                                }
+                                addInstr(result, IRInstruction(Opcode.SCS, returnRegSpec.dt, reg1=finalReturnRegister), null)
                             }
                             else -> {
                                 val branchOpcode = when(statusFlagResult) {
-                                    Statusflag.Pc -> Opcode.BSTCS
+                                    Statusflag.Pc -> throw AssemblyError("carry should be treated separately")
                                     Statusflag.Pz -> Opcode.BSTEQ
                                     Statusflag.Pv -> Opcode.BSTVS
                                     Statusflag.Pn -> Opcode.BSTNEG
@@ -498,6 +496,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                         }
                     }
                 }
+
                 return if(fcall.void)
                     ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
                 else if(fcall.type==DataType.FLOAT)
diff --git a/docs/source/todo.rst b/docs/source/todo.rst
index 7102eb6af..99f5b6a0b 100644
--- a/docs/source/todo.rst
+++ b/docs/source/todo.rst
@@ -1,10 +1,6 @@
 TODO
 ====
 
-IR: use SCC and SCS, to optimize some code that sets 0/1 based on carry flag status
-
-try to get rid of ArrayIndex class
-
 ...
 
 
diff --git a/examples/test.p8 b/examples/test.p8
index 17f13980b..a4bf0ed77 100644
--- a/examples/test.p8
+++ b/examples/test.p8
@@ -1,16 +1,26 @@
-%import floats
 %import textio
 %zeropage basicsafe
 %option no_sysinit
 
 main {
     sub start() {
-        &uword[30] wb = $2000
-        &uword[100] array1 = $9e00
-        &uword[30] array2 = &array1[len(wb)]
+        ubyte xx = wobwob()
+        txt.print_ub(xx)
+        uword yy = wobwob2()
+        txt.print_uw(yy)
 
-        txt.print_uwhex(&array1, true)           ; $9e00
-        txt.print_uwhex(&array1[len(wb)], true)  ; $9e3c
-        txt.print_uwhex(&array2, true)           ; $9e3c
+        asmsub wobwob() -> bool @Pc {
+            %asm {{
+                sec
+                rts
+            }}
+        }
+
+        asmsub wobwob2() -> bool @Pc {
+            %asm {{
+                clc
+                rts
+            }}
+        }
     }
 }